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1、1,Digital Logic Design and ApplicationChen YanLecture #2,UESTC, Spring 2011,Chapter 3 Digital Circuits Give a knowledge of the Electrical aspects of Digital Circuits,学习要求,2,掌握: CMOS逻辑电平和噪声容限;CMOS逻辑基本门的电路结构; 理解:CMOS逻辑电路的稳态和动态电气特性; 理解:特殊的输入输出电路结构; 了解:利用仿真软件对CMOS基本逻辑门的静态特性和动态特性进行仿真。 了解:作为电子开关运用的二极管、双极型

2、晶体管、MOS场效应管的工作方式; 了解:其他类型的逻辑电路:TTL,ECL等; 了解:不同类型、不同工作电压的逻辑电路的输入输出逻辑电平规范值以及它们之间的连接配合的问题。电路成本、速度与基本电路规模的关系。,3.1 Logic Signals and Gates,Digit logic hide the pitfalls of the analog world by mapping the infinite set of real values for a physical quantity into two subsets corresponding to just two possib

3、le numbers or logic :0 an 1,3,logical abstraction,3.1 Logic Signals and Gates,4,Tab. 3-1 the maping of practical physical signal to the logical signal,玩过碟仙、笔仙的游戏吗?,3.1 Logic Signals and Gates,5,Buffer amplifier,1,the minmial input high voltage level,voltage level,Weak,strong,3.1 Logic Signals and Ga

4、tes,6,3.1 Logic Signals and Gates,Methods of description, analysis and design the abstract logic circuits switching algebra Truth table/ State Table,7,X+X=X X*X=X ,8,Axioms of Logic Algebra,X = 0, if X 1 (若X 1, 则X = 0 ) X = 1, if X 0 (若X 0, 则X = 1) 0 = 11 = 0 0 0 = 01 + 1 = 1 1 1 = 10 + 0 = 0 01 = 1

5、0 = 01+0 = 0+1 = 1,9,Basic Logic Function AND,0 0 0 0 1 0 1 0 0 1 1 1,Logic Equation Z = A B,Switch: 1-on, 0-off Lamp: 1-light, 0-unlighted,An AND gate produces a 1 output if and only if all its inputs are 1 .,Truth Table,10,Basic Logic Function: OR,Logic Equation : Z = A + B,An OR gate produces a 1

6、 output if and only if one or more inputs is 1.,0 0 0 0 1 1 1 0 1 1 1 1,11,To produce an output value that is the opposite of its input value. Commonly called an Inverter.,Basic Logic Function: NOT,12,Truth Table,13,3.1 Logic Signals and Gates,The physical aspects of digital circuits Physical realiz

7、ation Working principles Electrical characters,Chap. 3,14,3.1 Logic Signals and Gates,How to get the HIGH and LOW Voltage?,Consult Fig. 3-62 for logical voltage comparetion,15,3.2 Logic Families,A logic family is a collection of different IC chips that have similar input, output, and internal circui

8、t characteristics, but that perform different logic functions. Chips of same family can be connected to perform arbitary logic function. (Fig. 6-62) Chips from different families may not be compatible. TTL families (Tab. 3-10) CMOS logic (Fig. 3-62),16,Some Terms,Semiconductor diode, 半导体二极管 Bipolar

9、junction transistor, 双极结型晶体管 Integrated circuit, 集成电路 Bipolar logic family, 双极型逻辑系列 Transistor-transistor logic, TTL, 晶体管-晶体管逻辑 Metal-oxide semiconductor field-effect transistor, MOSFET, 金属氧化物半导体场效应晶体管 Complementary MOS, CMOS, 互补MOS,17,3.3 CMOS Logic,1. CMOS Logic Levels,undefined logic level ,A CMO

10、S Logic Circuit uses not only 5-Volt power-supply voltage, but other power-supply voltages, such as 3.3, 2.7 volts.,18,2. MOS Transistors,Two Types: N-Channel and P-Channel,An input voltage controls the resistance between drain and source.,19,2. MOS Transistors,Normally, Vgs = 0 If Vgs = 0 Rds is ve

11、ry high ( 106 ) The transistor is “Off”. increase Vgs decrease Rds when Rds is very low ( =10 ) the transistor is “On”.,An input voltage controls the resistance between drain and source.,20,2. MOS Transistors,Two Types: P-Channel,Normally, Vgs = 0 If Vgs = 0 Rds is very high. The transistor is “Off”

12、. Vgs Rds when Rds is very low, the transistor is “On”.,An input voltage controls the resistance between drain and source.,注意,空穴的概念,以及空穴导电的实质还是电子导电。,2. MOS Transistors,Two Types MOS: N-Channel and P-Channel An input voltage controls the resistance between drain and source Rgs、Rgd is extremely high W

13、hatever voltage on Gate,igs, igd 0 (1A)is called Leakage current. There are capacitive coupling between the Gate T1 on, T2 off; Z=X S=1; T1 off, T2 On; Z=Y,T1,T2,43,2. Three-State Outputs,If EN=0, C=1, Tp=“off” B=1, D=0, Tn=“off” Z = Hi-impedance state or floating state If EN=1 C=A , B=0 , D=A Z=A (

14、 0 or 1 ),还有很多其他三态缓冲器件类型,其应用主要是三态总线,44,3. Open-Drain Outputs,As small as possible, to minimize the rise time. Cannot be arbitrarily small, it is determined by IOLmax,passive pull-up 无源上拉,Applications: driving multisource buses; driving LEDs; performing wired logic.,3. Open-Drain Outputs,45,Pull-up r

15、esistor value 上拉电阻阻值的范围,L,H,3. Open-Drain OutputsDriving LEDs,LED点亮的条件是:使Vz为低电压,与Vcc有1.6V的电压差,并且保证 ILED10mA,46,VOLmax,VCC=VLED+VOL +VR =VLED+VOL +R*ILED,R =,VCC-VLED -VOLMax,ILEDmin,47,3. Open-Drain OutputsMulti-source Buses,48,Z = Z1 Z2 = (AB) (CD) = (AB + CD),Wired Logic of Open-Drain Outputs,Wired AND (线与),49,2. 输出电平? 造成逻辑混乱,1.很大的负载电流同时流过输出级可使门电路损坏,3. Open-Drain Outputs,active pull-up 有源上拉,有源上拉的CMOS器件 其输出端不能直接相联,Fighting 冲突,50,4. Schmitt-Trigger Inputs,Use feedback i

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