u4f4stk14c88-3_W

1、STK14C88-332K x 8 AutoStore nvSRAM QuantumTrap CMOS Nonvolatile Static RAMNovember 20031Document Control # ML0015 rev 0.3FEATURES 35ns, 45ns and 55ns Access Times “Hands-off” Automatic STORE with External 68mF Capacitor on Power Down STORE to nonvolatile elements Initiated by Hardware, Software or A

2、utoStore RECALL to SRAM Initiated by Software or Power Restore 10mA Typical ICC at 200ns Cycle Time Unlimited READ, WRITE and RECALL Cycles 1,000,000 STORE Cycles to nonvolatile ele- ments (Commercial/Industrial) 100-Year Data Retention in nonvolatileele- ments (Commercial/Industrial) Single 3.3V +

3、0.3V Operation Commercial and Industrial Temperatures 32-Pin SOIC and DIP PackagesDESCRIPTIONThe Simtek STK14C88-3 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent, non- volatile

4、data resides in nonvolatile elements. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) can take place automatically on power down. A 68mF or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power fro

5、m “hot swapping”. Transfers from the nonvolatile elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initia- tion of STORE and RECALL cycles can also be soft- ware controlled by entering specific read sequences. A hardware STORE may be initiated with the HSB

6、 pin. Quantum Trap 512 x 512A5A6 A7 A8 A9 A11 A12 A13 A14 POWER CONTROLSTORERECALLSTORE/ RECALL CONTROLHSBQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7SOFTWARE A0 - A13 DETECTA0 A1 A2 A3 A4 A10GEWCOLUMN DECCOLUMN I/OBLOCK DIAGRAMPIN CONFIGURATIONSSTATIC RAM ARRAY 512 x 512ROW DECODERINPUT BUFFERSD D D D D D D DPIN NAMESV

7、CCX VCAPCAP A14 A12 A7 A6 A5 A4 A3 NCA2 A1 A0Q0 Q1 Q2 VSSVCCX HSB WA13 A8 A9 A11 GNCA10 EDQ7 DQ6 DQ5 DQ4 DQ33231302928272625242322212019181712345678910111213141516VD D D32 - DIP32 - SOIC48 - SSOPA0 - A14DQ0 -DQ7EWGHSBVCCXVCAPVSSAddress InputsData In/OutChip EnableWrite EnableOutput EnableHardware St

8、ore Busy (I/O)Power (+ 3.3V)CapacitorGround(not to scale)STK14C88-3ABSOLUTE MAXIMUM RATINGSaVoltage on Input Relative to GroundV to 4.5VVoltage on Input Relative to VSS0.6V to (VCC + 0.5V)Voltage on DQ0-7 or HSB0.5V to (VCC + 0.5V)Temperature under Bias55C to 125CStorage Temperature65C to 150CPower

9、Dissipation1WDC Output Current (1 output at a time, 1s duration)15mANote a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at con- ditions above those indicated in the

10、operational sections of this specification is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affectreliability.November 200313Document Control # ML0015 rev 0.3DC CHARACTERISTICS(VCC = 3.0V-3.6V)eSYMBOLPARAMETERCOMMERCIALINDUSTRIALUNITSNOTESMINMAXMINMAXICC b 1A

11、verage VCC Current504237524439mA mA mAtAVAV = 35ns tAVAV = 45ns tAVAV = 55nscICC2Average VCC Current during STORE33mAAll Inputs Dont Care, VCC = maxICC b 3Average VCC Current at tAVAV = 200ns 5V, 25C, Typical99mAW (V CC 0.2V)All Others Cycling, CMOS LevelsICC c 4Average VCAP Current duringAutoStore

12、Cycle22mAAll Inputs Dont CareISB d 1Average VCC Current(Standby, Cycling TTL Input Levels)181615191716mA mA mAtAVAV = 35ns, E VIH tAVAV = 45ns, E VIH tAVAV = 55ns, E VIHISB d 2VCC Standby Current(Standby, Stable CMOS Input Levels)11mAE (V CC 0.2V)All Others VIN 0.2V or (VCC 0.2V)IILKInput Leakage Cu

13、rrent11mAVCC = maxVIN = VSS to VCCIOLKOff-State Output Leakage Current11mAVCC = max VIN = VSS to VCC, E or G VIHVIHInput Logic “1” Voltage2.2VCC + .52.2VCC + .5VAll InputsVILInput Logic “0” VoltageVSS .50.8VSS .50.8VAll InputsVOHOutput Logic “1” Voltage2.42.4VIOUT = 4mA except HSBVOLOutput Logic “0”

14、 Voltage0.40.4VIOUT = 8mA except HSBVBLLogic “0” Voltage on HSB Output0.40.4VIOUT = 3mATAOperating Temperature070 4085CNote b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC2 and ICC4 are the average currents require

15、d for the duration of the respective STORE cycles (tSTORE ).Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.Note e: VCC reference levels throughout this datasheet refer to VCCX.351 OhmsInput Pulse LevelsV to 3VInput Rise and Fall Times. . .

16、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference LevelsVOutput LoadSee Figure 1AC TEST CONDITIONS3.3V317 OhmsCAPACITANCEf(TA = 25C, f = 1.0MHz)SYMBOLPARAMETERMAXUNITSCONDITIONSCINInput Capacitance5pFDV = 0 to 3VCOUTOutput Capacitance7pFDV = 0 to 3VNote

17、 f: These parameters are guaranteed but not tested.OUTPUT30 pF INCLUDING SCOPE AND FIXTUREFigure 1: AC Output LoadingSTK14C88-3SRAM READ CYCLES #1 & #2(VCC = 3.0V-3.6V)eNO.SYMBOLSPARAMETERSTK14C88-3-35STK14C88-3-45STK14C88-3-55UNITS#1, #2Alt.MINMAXMINMAXMINMAX1tELQVtACSChip Enable Access Time354555n

18、s2tAVAVgtRCRead Cycle Time354555ns3htAVQVtAAAddress Access Time354555ns4tGLQVtOEOutput Enable to Data Valid152025ns5htAXQXtOHOutput Hold after Address Change555ns6tELQXtLZChip Enable to Output Active555ns7tEHQZitHZChip Disable to Output Inactive131520ns8tGLQXtOLZOutput Enable to Output Active000ns9t

19、GHQZitOHZOutput Disable to Output Inactive131520ns10tELICCHftPAChip Enable to Power Active000ns11ftEHICCLtPSChip Disable to Power Standby354555nsNote g: W and HSB must be high during SRAM READ cycles.Note h: I/O state asumes E and G VIH; device is continuously selected. Note i: Measured 200mV from s

20、teady state output voltage.SRAM READ CYCLE #1: Address Controlledg, htAVAV5 tAXQX 3 tAVQVDATA VALID2ADDRESSDQ (DATA OUT)2 tAVAV1 tELQV 11 tEHICCL 6tELQX7 tEHQZ9 tGHQZ8 tGLQX4 tGLQVDATA VALID10 tELICCHACTIVE STANDBYSRAM READ CYCLE #2: E ControlledgADDRESSEGDQ (DATA OUT)ICCSTK14C88-3SRAM WRITE CYCLES

21、#1 & #2(VCC = 3.0V-3.6V)eNO.SYMBOLSPARAMETERSTK14C88-3-35STK14C88-3-45STK14C88-3-55UNITS#1#2Alt.MINMAXMINMAXMINMAX12tAVAVtAVAVtWCWrite Cycle Time354555ns13tWLWHtWLEHtWPWrite Pulse Width253040ns14tELWHtELEHtCWChip Enable to End of Write253040ns15tDVWHtDVEHtDWData Set-up to End of Write121525ns16tWHDX

22、tEHDXtDHData Hold after End of Write000ns17tAVWHtAVEHtAWAddress Set-up to End of Write253040ns18tAVWLtAVELtASAddress Set-up to Start of Write000ns19tWHAXtEHAXtWRAddress Hold after End of Write000ns20tWLQZi, jtWZWrite Enable to Output Disable131520ns21tWHQXtOWOutput Active after End of Write555nsNote

23、 j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be VIH during address transitions.Note l: HSB must be high during SRAM WRITE cycles.SRAM WRITE CYCLE #1: W Controlledk, ltAVAVADDRESS14 tELWH19 tWHAXE17 tAVWH W18 tAVWL13 tWLWH15 tDVWHDATA VALID16 tW

24、HDXDATA IN20 tWLQZ21 tWHQXDATA OUTPREVIOUS DATAHIGH IMPEDANCE12DATA INSRAM WRITE CYCLE #2: E Controlledk, lADDRESS12 tAVAV18 tAVELE14 tELEH19 tEHAXWDATA IN17 tAVEH13 tWLEH15 tDVEHDATA VALID16 tEHDXDATA OUTHIGH IMPEDANCESTK14C88-3HARDWARE MODE SELECTIONEWHSBA13 - A0 (hex)MODEI/OPOWERNOTESHXHXNot Sele

25、ctedOutput High ZStandbyLHHXRead SRAMOutput DataActivetLLHXWrite SRAMInput DataActiveXXLXNonvolatile STOREOutput High ZlCC2mNote m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode,

26、 inhibiting all operations until HSB rises.HARDWARE STORE CYCLE(VCC = 3.0V-3.6V)eNO.SYMBOLSPARAMETERSTK14C88-3UNITSNOTESStandardAlternateMINMAX22tSTOREtHLHZSTORE Cycle Duration10msi, n23tDELAYtHLQZTime Allowed to Complete SRAM Cycle1msi, n24tRECOVERtHHQXHardware STORE High to Inhibit Off700nsn, o25t

27、HLHXHardware STORE Pulse Width15ns26tHLBLHardware STORE Low to STORE Busy300nsNote n: E and G low and W high for output behavior.Note o: tRECOVER is only applicable after tSTORE is complete.HARDWARE STORE CYCLE25 tHLHXHSB (IN)24 tRECOVER22 tSTOREHSB (OUT)HIGH IMPEDANCE26 tHLBLHIGH IMPEDANCEDQ (DATA

28、OUT)23 tDELAYDATA VALIDDATA VALIDSTK14C88-3AutoStore/POWER-UP RECALL(VCC = 3.0V-3.6V)eNO.SYMBOLSPARAMETERSTK14C88-3UNITSNOTESStandardAlternateMINMAX27tRESTOREPower-up RECALL Duration550msp28tSTOREtHLHZSTORE Cycle Duration10msn, q29tVSBLLow Voltage Trigger (VSWITCH) to HSB Low300nsl30tDELAYtBLQZTime

29、Allowed to Complete SRAM Cycle1msn31VSWITCHLow Voltage Trigger Level2.72.95V32VRESETLow Voltage Reset Level2.4VNote p: tRESTORE starts from the time VCC rises above VSWITCH.Note q: HSB is asserted low for 1ms when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvol

30、atile cycle, HSB will be released and no STORE will take place.AutoStore/POWER-UP RECALLVCC31VSWITCH32VRESETAutoStorePOWER-UP RECALL27t29 tVSBL 28 tSTOREHSBWRESTORE30 tDELAYDQ (DATA OUT)POWER-UPRECALLBROWN OUT NO STORE(NO SRAM WRITES)NO RECALL (VCC DID NOT GO BELOW VRESET)BROWN OUTAutoStoreNO RECALL

31、 (VCC DID NOT GO BELOW VRESET)BROWN OUTAutoStoreRECALL WHEN VCC RETURNS ABOVE VSWITCHSTK14C88-3SOFTWARE STORE/RECALL MODE SELECTIONEWA13 - A0 (hex)MODEI/OPOWERNOTES0E38Read SRAMOutput Data31C7Read SRAMOutput DataLH03E03C1FRead SRAM Read SRAMOutput Data Output DataActiver, s, t303F0FC0Read SRAM Nonvo

32、latile STOREOutput Data Output High ZlCC20E38Read SRAMOutput Data31C7Read SRAMOutput DataLH03E03C1FRead SRAM Read SRAMOutput Data Output DataActiver, s, t303F0C63Read SRAM Nonvolatile RECALLOutput Data Output High ZSOFTWARE-CONTROLLED STORE/RECALL CYCLEv(VCC = 3.0V-3.6V)eNO.SYMBOLSPARAMETERSTK14C88-

33、3-25STK14C88-3-35STK14C88-3-45UNITSNOTESStandardAlternateMINMAXMINMAXMINMAX33tAVAVtRCSTORE/RECALL Initiation Cycle Time354555nsn34tAVELtASAddress Set-up Time000nsu35tELEHtCWClock Pulse Width253045nsu36tELAXAddress Hold Time202020nsu37tRECALLRECALL Duration202020msNote r: The six consecutive addresse

34、s must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note s: While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.Note t: I/O state assumes G VIL. Activation of nonvolatile cycles does not depen

35、d on state of G. Note u: The software sequence is clocked with E controlled READs.Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle.

36、 W must be high during all six consecutive cycles.SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDv 33 tAVAVADDRESSADDRESS #133tAVAVADDRESS #6 34 35tAVELEtELEH36tELAXt 28 / t 37DATA VALIDDATA VALIDSTORE RECALLDQ (DATADATA VALIDHIGH IMPEDANCESTK14C88-3 DEVICE OPERATIONThe STK14C88-3 has two separate modes o

37、f opera- tion: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to nonvolatile elements (the STORE operation) or from nonvolatile elements to SRAM (the RECALL operation). In this mode SRAM func- tions

38、are disabled.NOISE CONSIDERATIONSThe STK14C88-3 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1mF connected between VCAP and VSS, using leads and traces that are as short as pos- sible. As with all high-speed CMOS ICs, normal care- ful routing of power,

39、 ground and signals will help prevent noise problems.SRAM READThe STK14C88-3 performs a READ cycle whenever E and G are low and W and HSB are high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the

40、 out- puts will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time with- out the need for tra

41、nsitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low.SRAM WRITEA WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and mu

42、st remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE.It is recommended that G be kept high during the

43、entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.POWER-UP RECALLDuring power up, or after any low-power condition (VCAP VRESET), an internal RECALL request will be latched. When VCAP once

44、 again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete.If the STK14C88-3 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected ei

45、ther between W and system VCC or between E and system VCC.SOFTWARE NONVOLATILE STOREThe STK14C88-3 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first perform

46、ed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed.Because a sequence of READs from specific addresses is used for STORE initiat

47、ion, it is impor- tant that no other READ or WRITE accesses inter- vene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place.To initiate the software STORE cycle, the followingREAD sequence must be performed:1. Read address0E38 (hex)Valid READ2. Read address31C7 (h

48、ex)Valid READ3. Read address03E0 (hex)Valid READ4. Read address3C1F (hex)Valid READ5. Read address303F (hex)Valid READ6. Read address0FC0 (hex)Initiate STORE cycleThe software sequence must be clocked with E con- trolled READs.Once the sixth address in the sequence has been entered, the STORE cycle

49、will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE ope

50、ration. STK14C88-310kW*1323130+1617SOFTWARE NONVOLATILE RECALL68m F6v, 20%0.1m FBypass10kWA software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the soft- ware STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ opera- tions must be performed:1. Read address0E38 (hex)Valid READ2. Read address31C7 (hex)Valid READ3. Read address03E0 (hex)Valid READ4. Read address3C1F (hex)Valid READ5. Read address303F (hex)Valid READ6. Read address0C63 (hex)Initiate RECALL cycleInternally, RECALL is a t