dc synopsys workshoppptdc1_200703_sg_01_intro

1、DesignCompiler 12007.03Synopsys Customer Education Services 2007 Synopsys, Inc. All Rights ReservedSynopsys 10-I-011-SSG-013Introductionsn Namen Companyn Job Responsibilitiesn EDA Experiencen Main Goal(s) and Expectations for this Course1- 2FacilitiesPlease turn off cell phones and pagers1- 3Buildin

2、g HoursPhonesEmergencyEXITMessagesRestroomsSmokingMealsRecyclingCurriculum FlowDesign Compiler Essentials for Place and RouteTThheePPoowweerrooffTTccl lT3hewoProkswheorposf Tcl33wwoorrkksshhooppssaatt 33 sskkilillllelveevleslsat 3 skill levelsPrimeTime: Debugging ConstraintsPrimeTime: Signal Integri

3、tyAstro 1JupiterXT 1DFTC 1TetraMAX 11- 4Physical Compiler 1PrimeTime 1IC Compiler 1Design Compiler 1Workshop GoalUse Synopsys Design Compiler to: Constrain a complex design for area and timing Apply synthesis techniques to achieve area and timing closure Analyze the results Generate design data that

4、 works with physical design or layout tools1- 5Target AudienceASIC digital designers with little or no Design Compiler experience.1- 6Workshop PrerequisitesYou should have knowledge of the following: Digital Logic UNIX and X-Windows A Unix based text editor1- 7What Does “Synthesis” Mean?1- 8Synthesi

5、s is the transformation of an idea into a manufacturable device to carry out an intended function.What do WE Mean by “Synthesis”?Our focus will be here.Synthesis1- 9Physical DeviceSiliconBehavioralHDL and simulation languageFunctionalGraphical or textual descriptionGate-Level NetlistRegister Transfe

6、rArchitectural HDLIdeaIdea captured on back of envelopeDesign Compiler FlowS Y N T H E S IS1- 10Write out designdataSynthesize the designSelect appropriate compile flowApply design constraintsCreate constraints fileCreate start-up fileLoad designs and librariesWrite RTL code and simulateSynthesis Tr

7、ansformations1Translate (read_verilogread_vhdl)3Optimize + Map (compile)Constrain (source)2Generic Boolean Gates(GTECH or unmapped ddc format)Technology-specific Gatesddc) (mapped ddc format)1- 114Save (write fThe verb “to compile” is used synonymously with “to synthesize”4x3x2x8x2x1xConstraintsset_

8、max_area create_clock . set_input_delay e;residue = 16h0000;RTL Sourcif (high_bits = 2b10)residue = state_tableindex; elsestate_tableindex = 16h0000Synthesis = Translation + Logic Optimization + Gate MappingSynthesis Is Constraint-Driven1- 12Design Compiler optimizes the design to meet your goals.Yo

9、u set the goals (through constraints).LargeAreaSmallShortDelayLongThree Interfaces to Design CompilerDesign Vision (interactive GUI)1DC Shell (interactive shell)2Batch mode31- 13unix% dc_shell-t f RUN.tcl | tee i my.logunix% dc_shell-tdc_shell-xg-tDC invoked in TCL mode andXG modeunix% design_vision

10、What is XG Mode (versus DB Mode)?n XG mode uses optimized memory management techniques that increase the tools capacity and can reduce runtimen The following Synopsys synthesis tools support the new XG mode Design Compiler DFT Compiler Power Compiler Physical Compilern In XG mode, all synthesis tool

11、s use the tool command language (Tcl) XG mode does not support the dcsh command language1- 14What Changes in XG Mode?n Use the new binary .ddc format to save design netlists Use in the same way as the old .db formatn Convert old .db to .ddc for maximum benefit Use of the .db format for storing desig

12、ns is still possible, but highly discouraged - results in significant memory overhead1- 15UNIX% dc_shell-t; # Invoke DC in XG modedc_shell-xg-t read_db MYDES.db; # Reverts DC to DB mode dc_shell-xg-t write format ddc hierarchy -output MYDES.ddc dc_shell-xg-t exitUNIX% dc_shell-t; # re-invoke DC in X

13、G mode and read MYDES.ddcdc_shell-xg-t read_ddc MYDES.ddcdc_shell-xg-t write format ddc hierarchy output MYDES.ddcHelpful UNIX-like DC_Shell commandsFind the location and/or names of files1dc_shell-xg-t pwd; cd; lsShow the history of commands entered:dc_shell-xg-t historyRepeat last command:dc_shell

14、-xg-t !Execute command no. 7 from the history list:dc_shell-xg-t !7Execute the last report command:dc_shell-xg-t !repExecute any UNIX command:dc_shell-xg-t sh Get any UNIX variable value:dc_shell-xg-t get_unix_variable21- 16AgendaDAY12341- 17Area and Timing ConstraintsDesign and Library ObjectsSetting Up and Saving DesignsIntroduction to Synthesis1AgendaDAY567891- 18More Constraint ConsiderationsTiming AnalysisCompile CommandsEnvironmental AttributesPartitioning for Synthesis2AgendaDAY9101112131- 19ConclusionPost-Synthesis Output DataSyn