lorawan协议栈及sx1301网关手册sx1301 datasheet

1、SX1301SX1301I/QDDDDRR-LLooRRaaDDR - LoRaTx/RxI/Q8xI/QI/Q(G)FSKtimestampPacket(G)FSK/LoRahandlerGeneral DescriptionThe SX1301 digital baseband chip is a massive digital signal processing engine specifically designed to offer breakthrough gateway capabilities in the ISM bands worldwide. It integrates

2、the LoRa concentrator IP.The LoRa concentrator is a multi-channel high performance transmitter/receiver designed to simultaneously receive several LoRa packets using random spreading factors on random channels. Its goal is to enable robust connection between a central wireless data concentrator and

3、a massive amount of wireless end-points spread over a very wide range of distances.The SX1301 is targeted at smart metering fixed networks and Internet of Things applications with up to 5000 nodes per km2 in moderately interfered environment.Key product featuresUp to -142.5 dBm sensitivity with SX12

4、57or SX1255 Tx/Rx front-end-140 dBm with included refdesign70 dB CW interferer rejection at1 MHz offsetAble to operate with negative SNRCCR up to 9 dBEmulates 49x LoRa demodulators and 1x(G)FSK demodulatorDual digital Tx & Rx radio front-endinterfaces10 programmable parallel demodulation pathsDynami

5、c data-rate adaptation (ADR) True antenna diversity or simultaneous dual-band operationApplicationsOrdering InformationSmart MeteringSecurity Sensors Network Agricultural Monitoring Internet of Things (IoT)V2.0 April 20141Packet handlerControlPart NumberConditioningSX1301IMLTRCTape & Reel 3,000 part

6、s per reelSX1301IMLTTraysMCUSPI(Tx/Rx)(GPS)LoRaWIRELESS, SENSING & TIMINGDatasheetSX1301Contents11.11.222.12.22.32.42.533.13.23.2.13.2.23.33.43.53.5.13.5.23.63.6.13.6.23.73.7.13.7.23.83.8.13.8.23.93.9.13.9.23.9.33.103.10.13.10.23.10.33.10.43.113.123.133.13.13.13.23.143.153.15.13.15.2PIN CONFIGURATIO

7、N7Pins placement and circuit marking7Pins description8ELECTRICAL CHARACTERISTICS10Absolute maximum ratings10Constraints on external10Operating conditions10Electrical specifications11Timing specifications11CIRCUIT OPERATION12General Presentation12Power-on12Power-up sequence12Setting the circuit is lo

8、w-power mode12Clocking13SPI Interface14Rx I/Q Interface15I/Q generated on clock rising edge15I/Q generated on clock falling edge15GPIO mapping16GPIO output configuration16GPIO input configuration16RX mode block diagram, reception paths characteristics17Block diagram17Reception paths characteristics1

9、7Packet engine and data buffers19Receiver Packet engine19Transmitter packet engine21Receiver IF frequencies configuration23Configuration using 2 x SX1257 radios23Two SX1255 : 433 MHz band25One SX1257 and one SX125525Connection to RF front-end26Connection to Semtech SX1255 or SX1257 components26SX130

10、1 RX operation using a third party RF front-end27Radio calibration29SX1301 connection to RF front-end for TX operation29Reference application30SX1301 sensitivity performance in reference application31SX1301 sensitivity vs data rate in LoRa mode31125kHz mode: IF8, IF0 to 7 paths31250 & 500 kHz mode:

11、IF8 only32SX1301 interference rejection32Hardware Abstraction Layer (HAL)34Introduction34Abstraction presented to the gateway host34V2.0 April 20142WIRELESS, SENSING & TIMINGDatasheetSX13013.15.33.15.43.15.544.14.24.2.14.2.24.2.34.2.45677.17.27.38Composition of the software library36Interaction with

12、 the Lora hardware37Important HAL functions39MEMORY MAP40Registers list40Registers Description43All pages registers43Page 0 registers45Page 1 registers48Page 2 registers51EXTERNAL COMPONENTS54PCB LAYOUT CONSIDERATIONS55PACKAGING INFORMATION58Package Outline Drawing58Thermal impedance of package58Lan

13、d Pattern Drawing59REVISION INFORMATION60FiguresFigure 1 Top view of SX1301 package with 64 pins and exposed ground paddle (bottom of package).7 Figure 2 Power-up sequence12Figure 3 SPI Timing Diagram (single access)14Figure 4 I/Q on clock rising edge15Figure 5 I/Q on clock falling edge15Figure 6 SX

14、1301 digital baseband chip block diagram17Figure 7 Access FIFO and data buffer20Figure 8 SX1255/57 digital I/Q power spectral density23Figure 9 Radio spectrum24Figure 10 Radio spectrum25Figure 11 Radio spectrum26Figure 12 Dual band operation27Figure 13 SX1301 with third party frontend28Figure 14 Dig

15、ital interface for third party radio28Figure 15 Transmission schematics29Figure 16 Reference application30Figure 17 CW interferer rejection SF733Figure 18 CW interferer rejection SF1233Figure 19 EPCOS B3117 SAW filter transfer function34Figure 20 PCB layout example57Figure 21 Package dimensions58Fig

16、ure 22 Land pattern drawing59TablesTable 1 Pins name and description9Table 2 Absolute maximum ratings10V2.0 April 20143WIRELESS, SENSING & TIMINGDatasheetSX1301Table 3 Externals10Table 4 Operating conditions for electrical specifications10Table 5 Electrical specifications11Table 6 Timing specificati

17、ons11Table 7 GPIO output configuration16Table 8 GPIO input configuration16Table 9 Packet data fields21Table 10 Packet structure for transmission23Table 11 IF frequencies set24Table 12 IF frequency used25Table 13 SX1301 performance in reference application31Table 14 Sensitivity with 125 kHz mode31Tab

18、le 15 Sensitivity with 250 kHz mode32Table 16 Sensitivity with 500 kHz mode32Table 17 HAL main data structures39Table 18 HAL main functions39Table 19 List of registers that are accessed without paging40Table 20 List of registers on page 041Table 21 List of registers on page 142Table 22 List of regis

19、ters on page 243Table 23 RegPage definition43Table 24 RegVer definition43Table 25 RegRdbal definition43Table 26 RegRdbah definition43Table 27 RegRdbd definition43Table 28 RegTdba definition44Table 29 RegTdbd definition44Table 30 RegMpd definition44Table 31 RegRpns definition44Table 32 RegRpapl defin

20、ition44Table 33 RegRpaph definition44Table 34 RegRps definition44Table 35 RegRpps definition44Table 36 RegGen definition44Table 37 RegCken definition44Table 38 RegGpsi definition44Table 39 RegGpso definition45Table 40 RegGpmode definition45Table 41 RegGpregi definition45Table 42 RegGprego definition

21、45Table 43 RegAgcsts definition45Table 44 RegArbsts definition45Table 45 RegId definition45Table 46 RegIqcfg definition45Table 47 RegDeccfg definition45Table 48 RegChrs definition45Table 49 RegIf0l definition45Table 50 RegIf0h definition45Table 51 RegIf1l definition45V2.0 April 20144WIRELESS, SENSIN

22、G & TIMINGDatasheetSX1301Table 52 RegIf1h definition46Table 53 RegIf2l definition46Table 54 RegIf2h definition46Table 55 RegIf3l definition46Table 56 RegIf3h definition46Table 57 RegIf4l definition46Table 58 RegIf4h definition46Table 59 RegIf5l definition46Table 60 RegIf5h definition46Table 61 RegIf

23、6l definition46Table 62 RegIf6h definition46Table 63 RefIf7l definition46Table 64 RegIf7h definition46Table 65 RegIf8l definition46Table 66 RegIf8h definition46Table 67 RegIf9l definition46Table 68 RegIf9h definition47Table 69 RegCore0deten definition47Table 70 RegCore1deten definition47Table 71 Reg

24、Core2deten definition47Table 72 RegCore3deten definition47Table 73 RegCore4deten definition47Table 74 RegCore5deten definition47Table 75 RegCore6deten definition47Table 76 RegCore7deten definition47Table 77 RegAmso124h definition47Table 78 RegTimtrak2 definition47Table 79 RegPrsymbnbl definition47Ta

25、ble 80 RegSymbnbh definition47Table 81 RegMisc_cfg2 definition47Table 82 RegHeader_cfg1 definition48Table 83 RegHeader_cfg2 definition48Table 84 RegMcu_ctrl definition48Table 85 RegChann_select_rssi definition48Table 86 RegTrig definition48Table 87 RegTx_offset_i definition48Table 88 RegTx_offset_q

26、definition48Table 89 RegBhimpcfg1 definition48Table 90 RegBhimpcfg2 definition48Table 91 RegBhsyncpos definition49Table 92 RegBhprsymnbl definition49Table 93 RegMbwssf_misc_cfg1 definition49Table 94 RegMbwssf_misc_cfg2 definition49Table 95 RegMbwssf_misc_cfg3 definition49Table 96 RegMbwssf_misc_cfg4

27、 definition49Table 97 RegTx_status definition49Table 98 RegFsx_cfg definition49Table 99 RegFsk_cfg2 definition49Table 100 RegFsk_error_osr_tol definition50V2.0 April 20145WIRELESS, SENSING & TIMINGDatasheetSX1301Table 101 RegFsk_br_ratiol definition50Table 102 RegFsk_br_ratioh definition50Table 103

28、RegFsk_ref_pattern_0 definition50Table 104 RegFsk_ref_pattern_1 definition50Table 105 RegFsk_ref_pattern_2 definition50Table 106 RegFsk_ref_pattern_3 definition50Table 107 RegFsk_ref_pattern_4 definition50Table 108 RegFsk_ref_pattern_5 definition50Table 109 RegFsk_ref_pattern_6 definition50Table 110

29、 RegFsk_ref_pattern_7 definition50Table 111 RegFsk_pkt_length definition50Table 112 RegFsk_aafc definition50Table 113 RegFsk_pattern_timeout_cfg definition50Table 114 RegFsk_pattern_timeout_cfg definition51Table 115 RegRadio_a_spi_1 definition51Table 116 RegRadio_a_spi_2 definition51Table 117 RegRad

30、io_a_spi_3 definition51Table 118 RegRadio_a_spi_4 definition51Table 119 RegRadio_b_spi_1 definition51Table 120 RegRadio_b_spi_2 definition51Table 121 RegRadio_b_spi_3 definition51Table 122 RegRadio_b_spi_4 definition51Table 123 RegRadio_cfg definition51Table 124 RegPa_gain definition51Table 125 RegF

31、e_a_ctrl_lut definition52Table 126 RegFe_b_ctrl_lut definition52Table 127 RegValid_header_counter_mbwssf definition52Table 128 RegValid_header_counter_fsk definition52Table 129 RegValid_packet_counter_mbwssf definition52Table 130 RegValid_packet_counter_fsk definition52Table 131 RegChann_rssi defini

32、tion52Table 132 RegBb_rssi definition52Table 133 RegDec_rssi definition52Table 134 RegTimestamp_0 definition52Table 135 RegTimestamp_1 definition52Table 136 RegTimestamp_2 definition52Table 137 RegTimestamp_3 definition53Table 138 RegSpi_master_cfg definition53Table 139 RegGps_cfg definition53Table

33、140 Recommended external components54V2.0 April 20146WIRELESS, SENSING & TIMINGDatasheetSX13011Pin ConfigurationPins placement and circuit marking1.1Figure 1 Top view of SX1301 package with 64 pins and exposed ground paddle (bottom of package).The ground paddle must be connected to ground potential

34、through a large conductive plane thatalso serves for temperature dissipation.V2.0 April 2014717643249148SX1301yywwxxxxxxxx1633Legend: yyww is the date code and xxxxxxxx is the Semtech lot number.WIRELESS, SENSING & TIMINGDatasheetSX13011.2Pins descriptionThe table below gives the description of the

35、pins of the circuit.V2.0 April 20148PinPin NameTypeDescription0VSSPower (GND)Ground paddle must be connected to ground for thermal dissipation1RESETInputGlobal asynchronous reset2HOST_SCKInputHOST SPI clock (max 10 MHz clock)3HOST_MISOOutputHOST SPI Interface4HOST_MOSIInputHOST SPI Interface5HOST_CS

36、NInputHOST SPI Interface6SCANMODEInputScanmode signal (tied to 0 in normal mode)7VSSPower (GND)Ground8VCC18Power (VDD)Logic core supply9GPS_INInputGPS 1 pps input10VSSPower (GND)Ground11VSSPower (GND)Ground12VCC18Power (VDD)Logic core supply13RADIO_A_ENOutputRadio A global enable14LNA_A_CTRLOutputLN

37、A A enable15PA_A_CTRLOutputPA A enable16NCNo connected tie to VSS17PA_GAIN1OutputPA gain control of both radio A/B18PA_GAIN0OutputPA gain control of both radio A/B19RADIO_B_CSOutputRadio B SPI interface20RADIO_B_MOSIOutputRadio B SPI interface21RADIO_B_MISOInputRadio B SPI interface22RADIO_B_SCKOutp

38、utRadio B SPI interface23VCC18Power (VCC)Logic core supply24VSSPower (GND)Ground25RADIO_RSTOutputRadio A/B global reset26PA_B_CTRLOutputPA B enable27LNA_B_CTRLOutputLNA B enable28RADIO_B_ENOutputRadio B global enable29VCC33Power (VCC)Logic IO supply30VSSPower (GND)Ground31VSSPower (GND)Ground32NCNo

39、connected tie to VSS33NCNo connected tie to VSS34SP_VALIDInputRadio C sample valid35B_IQ_RXInputRadio B 1 bit I/Q Rx samples36B_QI_RXInputRadio B 1 bit Q/I Rx samples37B_IQ_TXOutputRadio B 1 bit I/Q Tx samples38B_QI_TXOutputRadio B 1 bit Q/I Tx samples39SP_CLK_OUTOutputRadio C clock out (32 MHz)WIRE

40、LESS, SENSING & TIMINGDatasheetSX1301Table 1 Pins name and descriptionV2.0 April 20149PinPin NameTypeDescription40GNDPower (GND)Ground41GNDPower (GND)Ground42VCC18Power (VCC)Logic core supply43CLK32MInput32 MHz clock from radios crystal44A_IQ_RXInputRadio A 1 bit I/Q Rx samples45A_QI_RXInputRadio A

41、1 bit Q/I Rx samples46A_IQ_TXOutputRadio A 1 bit I/Q Tx samples47A_QI_TXOutputRadio A 1 bit Q/I Tx samples48NCNo connected tie to VSS49NCNo connected tie to VSS50VSSPower (GND)Ground51VSSPower (GND)Ground52VCC33Power (VCC)Logic IO supply53CLKHSInputHigh speed digital clock54GPIO4In/OutGeneral purpos

42、e GPIO455GPIO3In/OutGeneral purpose GPIO356GPIO2In/OutGeneral purpose GPIO257GPIO1In/OutGeneral purpose GPIO158GPIO0In/OutGeneral purpose GPIO059VSSPower (GND)Ground60VCC18Power (VCC)Logic core supply61RADIO_A_SCKOutputRadio A SPI interface62RADIO_A_MISOInputRadio A SPI interface63RADIO_A_MOSIOutput

43、Radio A SPI interface64RADIO_A_CSOutputRadio A SPI interfaceWIRELESS, SENSING & TIMINGDatasheetSX130122.1Electrical CharacteristicsAbsolute maximum ratingsStresses above the values listed below may cause permanent device failure. Exposure to absolutemaximum ratings for extended periods may affect de

44、vice reliability.parameters specified in the Operating Conditions section is not implied.OperationoutsidetheTable 2 Absolute maximum ratings2.2Constraints on externalCircuit is expected to be used with the following external conditions.Table 3 ExternalsOperating conditionsThe circuit will operate fu

45、ll specs within the following operating conditions.2.3Table 4 Operating conditions for electrical specificationsV2.0 April 201410ParameterSymbolConditionsMinTypMaxUnitDigital IO supplyVDDIOOperating Conditions for Electrical Specification3.03.6VDigital core supplyVDDCOREOperating Conditions for Elec

46、trical Specification1.751.85VOperating temperatureTJWith chip paddle soldered to PCB ground plan with minimum 100 cm2 air exposed area and heat sink-4085CParameterSymbolConditionsMinTypMaxUnitRadio ADC samples clock input frequencyXTAL32FClock for data communication with Tx32MHzADC sample clock freq

47、uency toleranceXTAL32T-10+10ppmHigh speed processing clockHSC_FClock for data processing130133150MHzLoad on IO pinsCLOP025pF The data communication IOs are A_I_RX, A_Q_RX, B_X_RX, B_Q_RX and clock signal is CLK32MNotes:ParameterSymbolConditionsValueIO power supply to VSSVDDIO,ABSMAX-0.5 V to 4.0 VCo

48、re power supply to VSSVDDCORE,ABSMAX-0.5 V to 2.0 VStorage temperatureTJ,STORE-50 C to 150 CAmbient operating temperatureTJ,ABSMAX-40 C to 125 CPin voltage on IO and Clock pinsVDPIN,ABSMAX-0.3 V to VDDIO + 0.3 VPeak reflow temperatureTPKG260 CLatchupILUPJESD78D, class I+/-100 mAHumidityHR0 95 %ESDHB

49、MHuman Body Model JESD22-A114 CLASS 22 kVCDMCharged Device Model JESD22-C101 CLASS III300 VWIRELESS, SENSING & TIMINGDatasheetSX13012.4Electrical specificationsThe table below gives the specifications of the circuit within the Operating Conditions as indicated in2.3 unless otherwise specified.Table

50、5 Electrical specifications2.5Timing specificationsThe table below gives the specifications of the circuit within the Operating Conditions as indicated in2.3 unless otherwise specified. See chapters 3.4 and 3.5 for timing diagrams and symbol definitions.Table 6 Timing specifications1 Idle current is reached following procedure indicated in application part of datasheet (chapter 3.2.2)V2.0 April 201411ParameterSymbolConditionsMinTypMaxUnitSPISCK frequencyFSCK-10MHzSCK high timetch50-nsSCK low t