4-datasheetuserguideg2452datasheet

1、MSP430G2x52 MSP430G2SLAS722E DECEMBER 2010 REVISED DECEMBER 2011MIXEDSIGNALMICROCONTROLLERFEATURESLow Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Active Mode: 220 A at 1 MHz, 2.2 V Standby Mode: 0.5 A Off Mode (RAM Retention): 0.1 A Five Power-Saving ModesUltra-Fast

2、 Wake-Up From Standby Mode in Less Than 1 s16-Bit RISC Architecture, 62.5-ns Instruction Cycle TimeBasic Clock Module ConfigurationsUniversal Serial Interface (USI) Supporting SPI and I2C10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan (MSP430G

3、2x52 Only)On-Chip Comparator for Analog Brownout DetectorSerial Onboard Programming,No External Programming Voltage Needed, Programmable Code Protection by Security FuseOn-Chip Emulation Logic With Spy-Bi-Wire InterfaceFamily Members are Summarized in Table 1 Package OptionsInternal Frequencies up t

4、o 16 MHz With Four Calibrated FrequenciesInternal Very-Low-Power Low-Frequency (LF) Oscillator32-kHz CrystalExternal Digital Clock SourceTSSOP: 14 Pin, 20 PinPDIP: 20 PinQFN: 16 PinOne 16-Bit Timer_A With Three Capture/Compare RegistersUp to 16 Touch-Sense Enabled I/O PinsFor Complete Module Descrip

5、tions, See theMSP430x2xx Family Users Guide (SLAU144)DESCRIPTIONThe Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optim

6、ized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mo

7、de in less than 1 s.The MSP430G2x52 and MSP430G2x12 series of microcontrollers are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, and up to 16 I/O touch sense enabled pins and built-in communication capability using the universal serial communication interface and have a

8、versatile analog comparator. The MSP430G2x52 series have a 10-bit A/D converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a hos

9、t system.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.MSP430 is a trademark of Texas Instruments.All other trademarks are

10、 the property of their respective owners.PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Copyright 20102011, Texas

11、Instruments IncorporatedMSP430G2x52 MSP430G2x12SLAS722E DECEMBER 2010 REVISED DECEMBER 2011Table 1. Available Options(1)(1)For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at .Package drawin

12、gs, thermal data, and symbolization are available at /packaging.(2)2Submit Documentation FeedbackCopyright 20102011, Texas Instruments IncorporatedDeviceEEMFlash (KB)RAM (B)Timer_AComp_A ChannelADC10ChannelUSIClockI/OPackage Type(2)MSP430G2452IN20 MSP430G2452IPW20 MSP430G2452IRSA16MSP430G2

13、452IPW14182561x TA3881LF, DCO, VLO1616101020-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2352IN20 MSP430G2352IPW20 MSP430G2352IRSA16MSP430G2352IPW14142561x TA3881LF, DCO, VLO1616101020-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2252IN20 MSP430G2252IPW20 MSP430G2252IRSA16MSP430G2252IPW14122561x TA3881LF, DCO, VLO16161010

14、20-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2152IN20 MSP430G2152IPW20 MSP430G2152IRSA16MSP430G2152IPW14111281x TA3881LF, DCO, VLO1616101020-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2412IN20 MSP430G2412IPW20 MSP430G2412IRSA16MSP430G2412IPW14182561x TA38-1LF, DCO, VLO1616101020-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2312IN

15、20 MSP430G2312IPW20 MSP430G2312IRSA16MSP430G2312IPW14142561x TA38-1LF, DCO, VLO1616101020-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2212IN20 MSP430G2212IPW20 MSP430G2212IRSA16MSP430G2212IPW14122561x TA38-1LF, DCO, VLO1616101020-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2112IN20 MSP430G2112IPW20 MSP430G2112IRSA16MSP43

16、0G2112IPW14111281x TA38-1LF, DCO, VLO1616101020-PDIP20-TSSOP16-QFN14-TSSOPMSP430G2x52 MSP430G2SLAS722E DECEMBER 2010 REVISED DECEMBER 2011DEVICE PINOUTSPW PACKAGE (TOP VIEW)DVCC P1.0/TA0CLK/ACLK/A0/CA0P1.1/TA0.0/A1/CA1 P1.2/TA0.1/A2/CA2 P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3 P1.4/TA0.2

17、/SMCLK/A4/VREF+/VEREF+/CA4/TCKP1.5/TA0.0/SCLK/A5/CA5/TMS1234567141312111098DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIOP1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLKNOTE:NOTE:ADC10 pin functions are available only on MSP430G2x52.The pulldown resistors of port pins

18、P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.RSA PACKAGE (TOP VIEW)16 15 14 13P1.0/TA0CLK/ACLK/A0/CA0P1.1/TA0.0/A1/CA1 P1.2/TA0.1/A2/CA2 P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA31231211109XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO45 6 7 8NOTE:NOTE:ADC10 pin

19、 functions are available only on MSP430G2x52.The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.N OR PW PACKAGE (TOP VIEW)DVCC P1.0/TA0CLK/ACLK/A0/CA0P1.1/TA0.0/A1/CA1 P1.2/TA0.1/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/TA0.

20、2/SMCLK/A4/VREF+/VEREF+/CA4/TCKP1.5/TA0.0/SCLK/A5/CA5/TMSP2.0 P2.1 P2.21234567891020191817161514131211DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIOP1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLKP2.5 P2.4P2.3NOTE: ADC10 pin functions are available only on MSP430G2x52.

21、Submit Documentation Feedback3Copyright 20102011, Texas Instruments IncorporatedP1.4/SMCLK/A4/VREF+/VEREF+/CA4/TCK P1.5/TA0.0/SCLK/A5/CA5/TMS P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK P1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDIDVCC AVCC DVSS AVSSMSP430G2x52 MSP430G2x12SLAS722E DECEMBER 2010 REVISED DECEMBER 2011www.

22、FUNCTIONAL BLOCK DIAGRAMSFunctional Block Diagram, MSP430G2x52XIN XOUTDVCCDVSSP1.xP2.xup to 88ACLKPort P2Port P1ADCClock SystemFlashRAMSMCLKup to 8 I/O Interrupt capability pullup/down resistors8 I/OInterrupt capability pullup/down resistors10-Bit8KB256B8 Ch.Autoscan 1 ch DMA4KB2KB1KB256B256B1

23、28BMCLK16MHz CPUMABMDBincl. 16 RegistersEmulation 2BPUSIWatchdog WDT+Timer0_A3Comp_A+Brownout ProtectionUniversal SerialJTAG3 CC8 ChannelsInterfaceRegistersInterface SPI, I2C15-BitRST/NMIPort P2. Two pins are available on the 14-pin and 16-pin package options. Eight pins are available on the 20-pin

24、package options.NOTE:Functional Block Diagram, MSP430G2x12XIN XOUTDVCCDVSSP1.xP2.xup to 88ACLKPort P1Port P2FlashClock SystemSMCLKup to 8 I/O InterruptRAM8 I/O8KBInterrupt capability pullup/down resistors4KB2KBcapability pullup/down resistors256BMCLK1KB16MHz CPUMABMDBincl. 16 RegistersEmulation 2BPU

25、SIWatchdog WDT+Timer0_A3Comp_A+Brownout ProtectionUniversal Serial InterfaceJTAGInterface3 CCRegisters8 Channels15-BitSPI, I2CRST/NMIPort P2. Two pins are available on the 14-pin and 16-pin package options. Eight pins are available on the 20-pin package options.NOTE:4Submit Documentation FeedbackCop

26、yright 20102011, Texas Instruments IncorporatedSpy-BiWireSpy-Bi WireMSP430G2x52 MSP430G2SLAS722E DECEMBER 2010 REVISED DECEMBER 2011TERMINAL FUNCTIONSTable 2. Terminal Functions(1) Available only on MSP430G2x52 devices.Submit Documentation Feedback5Copyright 20102011, Texas Instruments

27、IncorporatedTERMINALI/ODESCRIPTIONNAMENO.14PW16RSA20N, PWP1.0/ TA0CLK/ ACLK/A0/CA0212I/OGeneral-purpose digital I/O pin Timer0_A, clock signal TACLK input ACLK signal outputADC10 analog input A0(1)Comparator_A+, CA0 inputP1.1/ TA0.0/A1/CA1323I/OGeneral-purpose digital I/O pinTimer0_A, capture: CCI0A

28、 input, compare: Out0 output ADC10 analog input A1(1)Comparator_A+, CA1 inputP1.2/ TA0.1/A2/CA2434I/OGeneral-purpose digital I/O pinTimer0_A, capture: CCI1A input, compare: Out1 output ADC10 analog input A2(1)Comparator_A+, CA2 inputP1.3/ ADC10CLK/ CAOUT/A3/VREF-/VEREF/ CA3545I/OGeneral-purpose digi

29、tal I/O pin ADC10, conversion clock output(1) Comparator_A+, outputADC10 analog input A3(1)ADC10 negative reference voltage(1) Comparator_A+, CA3 inputP1.4/ SMCLK/ TA0.2/A4/ VREF+/VEREF+/ CA4/TCK656I/OGeneral-purpose digital I/O pin SMCLK signal outputTimer0_A, capture: CCI2A input, compare: Out2 ou

30、tput ADC10 analog input A4(1)ADC10 positive reference voltage(1) Comparator_A+, CA4 inputJTAG test clock, input terminal for device programming and testP1.5/ TA0.0/ SCLK/A5/ CA5/TMS767I/OGeneral-purpose digital I/O pin Timer0_A, compare: Out0 outputUSI: clk input in I2C mode; clk in/output in SPI mo

31、de ADC10 analog input A5(1)Comparator_A+, CA5 inputJTAG test mode select, input terminal for device programming and testP1.6/ TA0.1/ SDO/ SCL/A6/ CA6/TDI/TCLK8714I/OGeneral-purpose digital I/O pin Timer0_A, compare: Out1 output USI: Data output in SPI mode USI: I2C clock in I2C mode ADC10 analog inp

32、ut A6(1) Comparator_A+, CA6 inputJTAG test data input or test clock input during programming and testMSP430G2x52 MSP430G2x12SLAS722E DECEMBER 2010 REVISED DECEMBER 2011Table 2. Terminal Functions (continued)(2) TDO or TDI is selected via JTAG instruction.(3) If XOUT/P2.7 is used as an inpu

33、t, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset.6Submit Documentation FeedbackCopyright 20102011, Texas Instruments IncorporatedTERMINALI/ODESCRIPTIONNAMENO.14PW16RSA20N, PWP1.7/ CAOUT/ SDI/ SDA/A7/ CA7/TDO/TDI(2)9815I/

34、OGeneral-purpose digital I/O pin Comparator_A+, outputUSI: Data input in SPI mode USI: I2C data in I2C mode ADC10 analog input A7(1) Comparator_A+, CA7 inputJTAG test data output terminal or test data input during programming and testP2.0-8I/OGeneral-purpose digital I/O pinP2.1-9I/OGeneral-purpose d

35、igital I/O pinP2.2-10I/OGeneral-purpose digital I/O pinP2.3-11I/OGeneral-purpose digital I/O pinP2.4-12I/OGeneral-purpose digital I/O pinP2.5-13I/OGeneral-purpose digital I/O pinXIN/ P2.6/TA0.1131219I/OInput terminal of crystal oscillator General-purpose digital I/O pinTimer0_A, compare: Out1 output

36、XOUT/P2.7121118I/OOutput terminal of crystal oscillator(3)General-purpose digital I/O pinRST/ NMI/SBWTDIO10916IResetNonmaskable interrupt inputSpy-Bi-Wire test data input/output during programming and testTEST/SBWTCK111017ISelects test mode for JTAG pins on port 1. The device protection fuse is conn

37、ected to TEST.Spy-Bi-Wire test clock input during programming and testDVCC1161NASupply voltageAVCC-15-NASupply voltageDVSS141420NAGround referenceAVSS-13-NAGround referenceNC-NANot connectedQFN Pad-Pad-NAQFN package pad connection to VSS recommended.MSP430G2x52 MSP430G2SLAS722E DECEMBER

38、 2010 REVISED DECEMBER 2011SHORT-FORM DESCRIPTIONCPUThe MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand an

39、d four addressing modes for destination operand.The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- register operation execution time is one cycle of the CPU clock.Four of the registers, R0 to R3, are dedicated as program counter, stack pointer,

40、status register, and constant generator, respectively. The remaining registers are general-purpose registers.Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.The instruction set consists of the original 51 instructions with three f

41、ormats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R6R7R8R9R10R11R12Instruction SetThe instruction set consists of 51 instructions with three formats and seven address modes. Each

42、instruction can operate on word andbytedata. Table 3 shows examples of the three types of instruction formats; Table4 shows the address modes.R13R14R15Table 3. Instruction Word FormatsTable 4. Address Mode Descriptions(1)(1) S = source, D = destinationSubmit Documentation Feedback7Copyright 20102011

43、, Texas Instruments IncorporatedADDRESS MODESDSYNTAXEXAMPLEOPERATIONRegisterMOV Rs,RdMOV R10,R11R10 R11IndexedMOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5) M(6+R6)Symbolic (PC relative)MOV EDE,TONIM(EDE) M(TONI)AbsoluteMOV &MEM,&TCDATM(MEM) M(TCDAT)IndirectMOV Rn,Y(Rm)MOV R10,Tab(R6)M(R10) M(Tab+R6)Indirect

44、 autoincrementMOV Rn+,RmMOV R10+,R11M(R10) R11 R10 + 2 R10ImmediateMOV #X,TONIMOV #45,TONI#45 M(TONI)FORMATEXAMPLEOPERATIONDual operands, source-destinationADD R4,R5R4 + R5 - R5Single operands, destination onlyCALL R8PC (TOS), R8 PCRelative jump, un/conditionalJNEJump-on-equal bit = 0General-Purpose

45、 RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterConstant GeneratorStatus Re

46、gisterStack PointerProgram CounterMSP430G2x52 MSP430G2x12SLAS722E DECEMBER 2010 REVISED DECEMBER 2011Operating ModesThe MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service t

47、he request, and restore back to the low- power mode on return from the interrupt program.The following six operating modes can be configured by software:Active mode (AM) All clocks are active Low-power mode 0 (LPM0) CPU is disabled ACLK and SMCLK remain active, MCLK is disabled Low-power mode 1 (LPM

48、1)CPU is disabledACLK and SMCLK remain active, MCLK is disabledDCOs dc generator is disabled if DCO not used in active modeLow-power mode 2 (LPM2)CPU is disabledMCLK and SMCLK are disabled DCOs dc generator remains enabled ACLK remains activeLow-power mode 3 (LPM3)CPU is disabledMCLK and SMCLK are d

49、isabled DCOs dc generator is disabled ACLK remains activeLow-power mode 4 (LPM4)CPU is disabled ACLK is disabledMCLK and SMCLK are disabled DCOs dc generator is disabled Crystal oscillator is stopped8Submit Documentation FeedbackCopyright 20102011, Texas Instruments IncorporatedMSP430G2x52 MSP430G2x

50、12SLAS722E DECEMBER 2010 REVISED DECEMBER 2011Interrupt Vector AddressesThe interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the CPU goes into LPM4 immed