外文翻译--AT89S51概述.doc

THEDESCRIPTIONOFAT89S511GENERALDESCRIPTIONTHEAT89S51ISALOWPOWER,HIGHPERFORMANCECMOS8BITMICROCONTROLLERWITH4KBYTESOFINSYSTEMPROGRAMMABLEFLASHMEMORYTHEDEVICEISMANUFACTUREDUSINGATMEL’SHIGHDENSITYNONVOLATILEMEMORYTECHNOLOGYANDISCOMPATIBLEWITHTHEINDUSTRYSTANDARD80C51INSTRUCTIONSETANDPINOUTTHEONCHIPFLASHALLOWSTHEPROGRAMMEMORYTOBEREPROGRAMMEDINSYSTEMORBYACONVENTIONALNONVOLATILEMEMORYPROGRAMMERBYCOMBININGAVERSATILE8BITCPUWITHINSYSTEMPROGRAMMABLEFLASHONAMONOLITHICCHIP,THEATMELAT89S51ISAPOWERFULMICROCONTROLLERWHICHPROVIDESAHIGHLYFLEXIBLEANDCOSTEFFECTIVESOLUTIONTOMANYEMBEDDEDCONTROLAPPLICATIONSTHEAT89S51PROVIDESTHEFOLLOWINGSTANDARDFEATURES4KBYTESOFFLASH,128BYTESOFRAM,32I/OLINES,WATCHDOGTIMER,TWODATAPOINTERS,TWO16BITTIMER/COUNTERS,AFIVEVECTORTWOLEVELINTERRUPTARCHITECTURE,AFULLDUPLEXSERIALPORT,ONCHIPOSCILLATOR,ANDCLOCKCIRCUITRYINADDITION,THEAT89S51ISDESIGNEDWITHSTATICLOGICFOROPERATIONDOWNTOZEROFREQUENCYANDSUPPORTSTWOSOFTWARESELECTABLEPOWERSAVINGMODESTHEIDLEMODESTOPSTHECPUWHILEALLOWINGTHERAM,TIMER/COUNTERS,SERIALPORT,ANDINTERRUPTSYSTEMTOCONTINUEFUNCTIONINGTHEPOWERDOWNMODESAVESTHERAMCONTENTSBUTFREEZESTHEOSCILLATOR,DISABLINGALLOTHERCHIPFUNCTIONSUNTILTHENEXTEXTERNALINTERRUPTORHARDWARERESET2PORTSPORT0ISAN8BITOPENDRAINBIDIRECTIONALI/OPORTASANOUTPUTPORT,EACHPINCANSINKEIGHTTTLINPUTSWHEN1SAREWRITTENTOPORT0PINS,THEPINSCANBEUSEDASHIGHIMPEDANCEINPUTSPORT0CANALSOBECONFIGUREDTOBETHEMULTIPLEXEDLOWORDERADDRESS/DATABUSDURINGACCESSESTOEXTERNALPROGRAMANDDATAMEMORYINTHISMODE,P0HASINTERNALPULLUPSPORT0ALSORECEIVESTHECODEBYTESDURINGFLASHPROGRAMMINGANDOUTPUTSTHECODEBYTESDURINGPROGRAMVERIFICATIONEXTERNALPULLUPSAREREQUIREDDURINGPROGRAMVERIFICATIONPORT1ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT1OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT1PINS,THEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT1PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEINTERNALPULLUPSPORT1ALSORECEIVESTHELOWORDERADDRESSBYTESDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT2ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT2OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT2PINS,THEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT2PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEINTERNALPULLUPSPORT2EMITSTHEHIGHORDERADDRESSBYTEDURINGFETCHESFROMEXTERNALPROGRAMMEMORYANDDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE16BITADDRESSESMOVXDPTRINTHISAPPLICATION,PORT2USESSTRONGINTERNALPULLUPSWHENEMITTING1SDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE8BITADDRESSESMOVXRI,PORT2EMITSTHECONTENTSOFTHEP2SPECIALFUNCTIONREGISTERPORT2ALSORECEIVESTHEHIGHORDERADDRESSBITSANDSOMECONTROLSIGNALSDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT3ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT3OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT3PINS,THEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT3PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEPULLUPSPORT3RECEIVESSOMECONTROLSIGNALSFORFLASHPROGRAMMINGANDVERIFICATIONPORT3ALSOSERVESTHEFUNCTIONSOFVARIOUSSPECIALFEATURESOFTHEAT89S51,ASSHOWNINTHEFOLLOWINGTABLE3SPECIALFUNCTIONREGISTERSAMAPOFTHEONCHIPMEMORYAREACALLEDTHESPECIALFUNCTIONREGISTERSFRSPACEISSHOWNINTABLE51NOTETHATNOTALLOFTHEADDRESSESAREOCCUPIED,ANDUNOCCUPIEDADDRESSESMAYNOTBEIMPLEMENTEDONTHECHIPREADACCESSESTOTHESEADDRESSESWILLINGENERALRETURNRANDOMDATA,ANDWRITEACCESSESWILLHAVEANINDETERMINATEEFFECTUSERSOFTWARESHOULDNOTWRITE1STOTHESEUNLISTEDLOCATIONS,SINCETHEYMAYBEUSEDINFUTUREPRODUCTSTOINVOKENEWFEATURESINTHATCASE,THERESETORINACTIVEVALUESOFTHENEWBITSWILLALWAYSBE0INTERRUPTREGISTERSTHEINDIVIDUALINTERRUPTENABLEBITSAREINTHEIEREGISTERTWOPRIORITIESCANBESETFOREACHOFTHEFIVEINTERRUPTSOURCESINTHEIPREGISTERDUALDATAPOINTERREGISTERSTOFACILITATEACCESSINGBOTHINTERNALANDEXTERNALDATAMEMORY,TWOBANKSOF16BITDATAPOINTERREGISTERSAREPROVIDEDDP0ATSFRADDRESSLOCATIONS82H83HANDDP1AT84H85HBITDPS0INSFRAUXR1SELECTSDP0ANDDPS1SELECTSDP1THEUSERSHOULDALWAYSINITIALIZETHEDPSBITTOTHEAPPROPRIATEVALUEBEFOREACCESSINGTHERESPECTIVEDATAPOINTERREGISTERPOWEROFFFLAGTHEPOWEROFFFLAGPOFISLOCATEDATBIT4PCON4INTHEPCONSFRPOFISSETTO“1”DURINGPOWERUPITCANBESETANDRESTUNDERSOFTWARECONTROLANDISNOTAFFECTEDBYRESET4MEMORYORGANIZATIONMCS51DEVICESHAVEASEPARATEADDRESSSPACEFORPROGRAMANDDATAMEMORYUPTO64KBYTESEACHOFEXTERNALPROGRAMANDDATAMEMORYCANBEADDRESSED41PROGRAMMEMORYIFTHEEAPINISCONNECTEDTOGND,ALLPROGRAMFETCHESAREDIRECTEDTOEXTERNALMEMORYONTHEAT89S51,IFEAISCONNECTEDTOVCC,PROGRAMFETCHESTOADDRESSES0000HTHROUGHFFFHAREDIRECTEDTOINTERNALMEMORYANDFETCHESTOADDRESSES1000HTHROUGHFFFFHAREDIRECTEDTOEXTERNALMEMORY42DATAMEMORYTHEAT89S51IMPLEMENTS128BYTESOFONCHIPRAMTHE128BYTESAREACCESSIBLEVIADIRECTANDINDIRECTADDRESSINGMODESSTACKOPERATIONSAREEXAMPLESOFINDIRECTADDRESSING,SOTHE128BYTESOFDATARAMAREAVAILABLEASSTACKSPACE7WATCHDOGTIMERONETIMEENABLEDWITHRESETOUTTHEWDTISINTENDEDASARECOVERYMETHODINSITUATIONSWHERETHECPUMAYBESUBJECTEDTOSOFTWAREUPSETSTHEWDTCONSISTSOFA14BITCOUNTERANDTHEWATCHDOGTIMERRESETWDTRSTSFRTHEWDTISDEFAULTEDTODISABLEFROMEXITINGRESETTOENABLETHEWDT,AUSERMUSTWRITE01EHAND0E1HINSEQUENCETOTHEWDTRSTREGISTERSFRLOCATION0A6HWHENTHEWDTISENABLED,ITWILLINCREMENTEVERYMACHINECYCLEWHILETHEOSCILLATORISRUNNINGTHEWDTTIMEOUTPERIODISDEPENDENTONTHEEXTERNALCLOCKFREQUENCYTHEREISNOWAYTODISABLETHEWDTEXCEPTTHROUGHRESETEITHERHARDWARERESETORWDTOVERFLOWRESETWHENWDTOVERFLOWS,ITWILLDRIVEANOUTPUTRESETHIGHPULSEATTHERSTPIN5USINGTHEWDTTOENABLETHEWDT,AUSERMUSTWRITE01EHAND0E1HINSEQUENCETOTHEWDTRSTREGISTERSFRLOCATION0A6HWHENTHEWDTISENABLED,THEUSERNEEDSTOSERVICEITBYWRITING01EHAND0E1HTOWDTRSTTOAVOIDAWDTOVERFLOWTHE14BITCOUNTEROVERFLOWSWHENITREACHES163833FFFH,ANDTHISWILLRESETTHEDEVICEWHENTHEWDTISENABLED,ITWILLINCREMENTEVERYMACHINECYCLEWHILETHEOSCILLATORISRUNNINGTHISMEANSTHEUSERMUSTRESETTHEWDTATLEASTEVERY16383MACHINECYCLESTORESETTHEWDTTHEUSERMUSTWRITE01EHAND0E1HTOWDTRSTWDTRSTISAWRITEONLYREGISTERTHEWDTCOUNTERCANNOTBEREADORWRITTENWHENWDTOVERFLOWS,ITWILLGENERATEANOUTPUTRESETPULSEATTHERSTPINTHERESETPULSEDURATIONIS98XTOSC,WHERETOSC1/FOSCTOMAKETHEBESTUSEOFTHEWDT,ITSHOULDBESERVICEDINTHOSESECTIONSOFCODETHATWILLPERIODICALLYBEEXECUTEDWITHINTHETIMEREQUIREDTOPREVENTAWDTRESETINPOWERDOWNMODETHEOSCILLATORSTOPS,WHICHMEANSTHEWDTALSOSTOPSWHILEINPOWERDOWNMODE,THEUSERDOESNOTNEEDTOSERVICETHEWDTTHEREARETWOMETHODSOFEXITINGPOWERDOWNMODEBYAHARDWARERESETORVIAALEVELACTIVATEDEXTERNALINTERRUPT,WHICHISENABLEDPRIORTOENTERINGPOWERDOWNMODEWHENPOWERDOWNISEXITEDWITHHARDWARERESET,SERVICINGTHEWDTSHOULDOCCURASITNORMALLYDOESWHENEVERTHEAT89S51ISRESETEXITINGPOWERDOWNWITHANINTERRUPTISSIGNIFICANTLYDIFFERENTTHEINTERRUPTISHELDLOWLONGENOUGHFORTHEOSCILLATORTOSTABILIZEWHENTHEINTERRUPTISBROUGHTHIGH,THEINTERRUPTISSERVICEDTOPREVENTTHEWDTFROMRESETTINGTHEDEVICEWHILETHEINTERRUPTPINISHELDLOW,THEWDTISNOTSTARTEDUNTILTHEINTERRUPTISPULLEDHIGHITISSUGGESTEDTHATTHEWDTBERESETDURINGTHEINTERRUPTSERVICEFORTHEINTERRUPTUSEDTOEXITPOWERDOWNMODETOENSURETHATTHEWDTDOESNOTOVERFLOWWITHINAFEWSTATESOFEXITINGPOWERDOWN,ITISBESTTORESETTHEWDTJUSTBEFOREENTERINGPOWERDOWNMODEBEFOREGOINGINTOTHEIDLEMODE,THEWDIDLEBITINSFRAUXRISUSEDTODETERMINEWHETHERTHEWDTCONTINUESTOCOUNTIFENABLEDTHEWDTKEEPSCOUNTINGDURINGIDLEWDIDLEBIT0ASTHEDEFAULTSTATETOPREVENTTHEWDTFROMRESETTINGTHEAT89S51WHILEINIDLEMODE,THEUSERSHOULDALWAYSSETUPATIMERTHATWILLPERIODICALLYEXITIDLE,SERVICETHEWDT,ANDREENTERIDLEMODEWITHWDIDLEBITENABLED,THEWDTWILLSTOPTOCOUNTINIDLEMODEANDRESUMESTHECOUNTUPONEXITFROMIDLETIMER0ANDTIMER1INTHEAT89S51OPERATETHESAMEWAYASTIMER0ANDTIMER1INTHEAT89C51FORFURTHERINFORMATIONONTHETIMERS’OPERATION,PLEASECLICKONTHEDOCUMENTLINKBELOWHTTP//WWWATMELCOM/DYN/RESOURCES/PROD_DOCUMENTS/DOC4316PDF6INTERRUPTSTHEAT89S51HASATOTALOFFIVEINTERRUPTVECTORSTWOEXTERNALINTERRUPTSINT0ANDINT1,TWOTIMERINTERRUPTSTIMERS0AND1,ANDTHESERIALPORTINTERRUPTTHESEINTERRUPTSAREALLSHOWNINFIGURE101EACHOFTHESEINTERRUPTSOURCESCANBEINDIVIDUALLYENABLEDORDISABLEDBYSETTINGORCLEARINGABITINSPECIALFUNCTIONREGISTERIEIEALSOCONTAINSAGLOBALDISABLEBIT,EA,WHICHDISABLESALLINTERRUPTSATONCENOTETHATTABLE101SHOWSTHATBITPOSITIONSIE6ANDIE5AREUNIMPLEMENTEDUSERSOFTWARESHOULDNOTWRITE1STOTHESEBITPOSITIONS,SINCETHEYMAYBEUSEDINFUTUREAT89PRODUCTSTHETIMER0ANDTIMER1FLAGS,TF0ANDTF1,ARESETATS5P2OFTHECYCLEINWHICHTHETIMERSOVERFLOWTHEVALUESARETHENPOLLEDBYTHECIRCUITRYINTHENEXTCYCLE7OSCILLATORCHARACTERISTICSXTAL1ANDXTAL2ARETHEINPUTANDOUTPUT,RESPECTIVELY,OFANINVERTINGAMPLIFIERTHATCANBECONFIGUREDFORUSEASANONCHIPOSCILLATOR,ASSHOWNINFIGURE111EITHERAQUARTZCRYSTALORCERAMICRESONATORMAYBEUSEDTODRIVETHEDEVICEFROMANEXTERNALCLOCKSOURCE,XTAL2SHOULDBELEFTUNCONNECTEDWHILEXTAL1ISDRIVEN,ASSHOWNINFIGURE112THEREARENOREQUIREMENTSONTHEDUTYCYCLEOFTHEEXTERNALCLOCKSIGNAL,SINCETHEINPUTTOTHEINTERNALCLOCKINGCIRCUITRYISTHROUGHADIVIDEBYTWOFLIPFLOP,BUTMINIMUMANDMAXIMUMVOLTAGEHIGHANDLOWTIMESPECIFICATIONSMUSTBEOBSERVED