外文翻译--AT89C52单片机.doc

TheAT89C52isalow-power,high-performanceCMOS8-bitmicrocomputerwith8KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).Thedeviceismanufac-turedusingAtmelshighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandard80C51and80C52instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C52isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.TheAT89C52providesthefollowingstandardfeatures:8KbytesofFlash,256bytesofRAM,32I/Olines,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89C52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/count-ers,serialport,andinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenexthard-warereset.Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable1.Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfea-tures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.Controlandstatusbitsarecontainedinreg-istersT2CONandT2MODforTimer2.Theregisterpair(RCAP2H,RCAP2L)aretheCapture/ReloadregistersforTimer2in16-bitcapturemodeor16-bitauto-reloadmode.TheindividualinterruptenablebitsareintheIEregister.Twoprioritiescanbesetforeachofthesixinter-ruptsourcesintheIPregister.TheAT89C52implements256bytesofon-chipRAM.Theup-per128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.Thatmeanstheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.Whenaninstructionaccessesaninternallocationaboveaddress7FH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspace.InstructionsthatusedirectaddressingaccessSFRspace.Forexample,thefollowingdirectaddressinginstructionac-cessestheSFRatlocation0A0H(whichisP2).MOV0A0H,#dataInstructionsthatuseindirectaddressingaccesstheupper128bytesofRAM.Forexample,thefollowingindirectaddressinginstruction,whereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanP2(whoseaddressis0A0H).MOVR0,#dataNotethatstackoperationsareexamplesofindirectaddressing,sotheupper128bytesofdataRAMareavailableasstackspace.Timer0and1Timer0andTimer1intheAT89C52operatethesamewayasTimer0andTimer1intheAT89C51.Timer2Timer2isa16-bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/T2intheSFRT2CON(showninTable2).Timer2hasthreeoperatingmodes:capture,auto-reload(upordowncount-ing),andbaudrategenerator.ThemodesareselectedbybitsinT2CON,asshowninTable3.Timer2consistsoftwo8-bitregisters,TH2andTL2.IntheTimerfunction,theTL2registerisincrementedeverymachinecycle.Sinceamachinecycleconsistsof12oscillatorperiods,thecountrateis1/12oftheoscillatorfrequency.IntheCounterfunction,theregisterisincrementedinresponsetoal-to-0transitionatitscorrespondingexternalinputpin,T2.Inthisfunction,theexternalinputissampledduringS5P2ofeverymachinecycle.Whenthesamplesshowahighinonecy-cleandalowinthenextcycle,thecountisincremented.ThenewcountvalueappearsintheregisterduringS3P1ofthecyclefollowingtheoneinwhichthetransitionwasdetected.Sincetwomachinecycles(24oscillatorperiods)arerequiredtorecog-nizea1-to-0transition,themaximumcountrateis1/24oftheoscillatorfrequency.Toensurethatagivenlevelissampledatleastoncebeforeitchanges,thelevelshouldbeheldforatleastonefullmachinecycle.CaptureModeInthecapturemode,twooptionsareselectedbybitEXEN2inT2CON.IfEXEN2=0,Timer2isa16-bittimerorcounterwhichuponoverflowsetsbitTF2inT2CON.Thisbitcanthenbeusedtogenerateaninterrupt.IfEXEN2=1,Timer2per-formsthesameoperation,butal-to-0transitionatexternalinputT2EXalsocausesthecurrentvalueinTH2andTL2tobecap-turedintoRCAP2HandRCAP2L,respectively.Inaddition,thetransitionatT2EXcausesbitEXF2inT2CONtobeset.TheEXF2bit,likeTF2,cangenerateaninterrupt.ThecapturemodeisillustratedinFigure1.Auto-Reload(UporDownCounter)Timer2canbeprogrammedtocountupordownwhenconfig-uredinits16-bitauto-reloadmode.ThisfeatureisinvokedbytheDCEN(DownCounterEnable)bitlocatedintheSFRT2MOD(seeTable4).Uponreset,theDCENbitissetto0sothattimer2willdefaulttocountup.WhenDCENisset,Timer2cancountupordown,dependingonthevalueoftheT2EXpin.Figure2showsTimer2automaticallycountingupwhenDCEN=0.Inthismode,twooptionsareselectedbybitEXEN2inT2CON.IfEXEN2=0,Timer2countsupto0FFFFHandthensetstheTF2bituponoverflow.Theoverflowalsocausesthetimerregisterstobereloadedwiththe16-bitvalueinRCAP2HandRCAP2L.ThevaluesinRCAP2HandRCAP2Larepresetbysoftware.IfEXEN2=1,a16-bitreloadcanbetriggeredeitherbyanoverfloworbyal-to-0transitionatexter-nalinputT2EX.ThistransitionalsosetstheEXF2bit.BoththeTF2andEXF2bitscangenerateaninterruptifenabled.SettingtheDCENbitenablesTimer2tocountupordown,asshowninFigure3.Inthismode,theT2EXpincontrolsthedi-rectionofthecount.Alogic1atT2EXmakesTimer2countup.Thetimerwilloverflowat0FFFFHandsettheTF2bit.Thisoverflowalsocausesthe16-bitvalueinRCAP2HandRCAP2Ltobereloadedintothetimerregisters,TH2andTL2,respectively.Alogic0atT2EXmakesTimer2countdown.Thetimerunder-flowswhenTH2andTL2equalthevaluesstoredinRCAP2HandRCAP2L.TheunderflowsetstheTF2bitandcauses0FFFFHtobereloadedintothetimerregisters.TheEXF2bittoggleswheneverTimer2overflowsorunder-flowsandcanbeusedasa17thbitofresolution.Inthisoperat-ingmode,EXF2doesnotflaganinterrupt.BaudRateGeneratorTimer2isselectedasthebaudrategeneratorbysettingTCLKand/orRCLKinT2CON(Table2).NotethatthebaudratesfortransmitandreceivecanbedifferentifTimer2isusedforthereceiverortransmitterandTimer1isusedfortheotherfunction.SettingRCLKand/orTCLKputsTimer2intoitsbaudrategen-eratormode,asshowninFigure4.Thebaudrategeneratormodeissimilartotheauto-reloadmode,inthatarolloverinTH2causestheTimer2registerstobere-loadedwiththe16-bitvalueinregistersRCAP2HandRCAP2L,whicharepresetbysoftware.TheTimercanbeconfiguredforeithertimerorcounteropera-tion.Inmostapplications,itisconfiguredfortimeroperation(CP/T2=0).ThetimeroperationisdifferentforTimer2whenitisusedasabaudrategenerator.Normally,asatimer,itincre-mentseverymachinecycle(at1/12theoscillatorfrequency).Asabaudrategenerator,however,itincrementseverystatetime(at1/2theoscillatorfrequency).Timer2asabaudrategeneratorisshowninFigure4.Thisfig-ureisvalidonlyifRCLKorTCLK=1inT2CON.NotethatarolloverinTH2doesnotsetTF2andwillnotgenerateaninter-rupt.Notetoo,thatifEXEN2isset,al-to-0transitioninT2EXwillsetEXF2butwillnotcauseareloadfrom(RCAP2H,RCAP2L)to(TH2,TL2).ThuswhenTimer2isinuseasabaudrategenerator,T2EXcanbeusedasanextraexternalinterrupt.NotethatwhenTimer2isrunning(TR2=1)asatimerinthebaudrategeneratormode,TH2orTL2shouldnotbereadfromorwrittento.Undertheseconditions,theTimerisincrementedeverystatetime,andtheresultsofareadorwritemaynotbeaccurate.TheRCAP2registersmaybereadbutshouldnotbewrittento,becauseawritemightoverlapareloadandcausewriteand/orreloaderrors.Thetimershouldbeturnedoff(clearTR2)beforeaccessingtheTimer2orRCAP2registers.ProgrammableClockOutA50%dutycycleclockcanbeprogrammedtocomeoutonP1.0,asshowninFigure5.Thispin,besidesbeingaregularI/0pin,hastwoalternatefunctions.ItcanbeprogrammedtoinputtheexternalclockforTimer/Counter2ortooutputa50%dutycycleclockrangingfrom61Hzto4MHzata16MHzoperatingfrequency.ToconfiguretheTimer/Counter2asaclockgenerator,bitC/T2(T2CON.1)mustbeclearedandbitT2OE(T2MOD.1)mustbeset.BitTR2(T2CON.2)startsandstopsthetimer.Theclock-outfrequencydependsontheoscillatorfrequencyandthereloadvalueofTimer2captureregisters(RCAP2H,RCAP2L).Intheclock-outmode,Timer2roll-overswillnotgenerateaninterrupt.ThisbehaviorissimilartowhenTimer2isusedasabaud-rategenerator.ItispossibletouseTimer2asabaud-rategeneratorandaclockgeneratorsimultaneously.Note,however,thatthebaud-rateandclock-outfrequenciescannotbedeter-minedindependentlyfromoneanothersincetheybothuseRCAP2HandRCAP2L.UARTTheUARTintheAT89C52operatesthesamewayastheUARTintheAT89C51.InterruptsTheAT89C52hasatotalofsixinterruptvectors:twoexternalinterrupts(INT0andINT1),threetimerinterrupts(Timers0,1,and2),andtheserialportinterrupt.TheseinterruptsareallshowninFigure6.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatTable5showsthatbitpositionIE.6isunimplemented.IntheAT89C51,bitpositionIE.5isalsounimplemented.Usersoftwareshouldnotwrite1stothesebitpositions,sincetheymaybeusedinfutureAT89products.Timer2interruptisgeneratedbythelogicalORofbitsTF2andEXF2inregisterT2CON.Neitheroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTF2orEXF2thatgeneratedtheinterrupt,andthatbitwillhavetobeclearedinsoftware.TheTimer0andTimer1flags,TF0andTFI,aresetatS5P2ofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.However,theTimer2flag,TF2,issetatS2P2andispolledinthesamecycleinwhichthetimeroverflows.OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure7.Eitheraquartzcrystalorce-ramicresonatormaybeused.Todrivethedevicefromanexter-nalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdriven,asshowninFigure8.Therearenorequire-mentsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.IdleModeInidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Notethatwhenidlemodeisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecutionfromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toeliminatethepossibilityofanunexpectedwritetoaportpinwhenidlemodeisterminatedbyareset,theinstructionfollow-ingtheonethatinvokesidlemodeshouldnotwritetoaportpinortoexternalmemoryPowerDownModeInthepowerdownmode,theoscillatorisstopped,andthein-structionthatinvokespowerdownisthelastinstructionexe-cuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminated.Theonlyexitfrompowerdownisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.ProgramMemoryLockBitsTheAT89C52hasthreelockbitsthatcanbeleftunprogrammed(U)orcanbeprogrammed