锡林右轴承座组件工艺及夹具设计机械毕业设计带CAD图
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外文翻译资料Monolithically integrated MEMS technology单片集成MEMS技术In the past 20 years, CMOS technology has become a major integrated circuit manufacturing technology, manufacturing costs decline at the same time, yield and production has also been greatly improved, COMS technology will continue to increase integration and reduce development of a special size. Today, CMOS integrated process not only be used in the design of integrated circuits, but also to be used in many micro-sensors and micro-actuator, so it can be integrated circuits and micro-sensor integrated with a powerful, intelligent sensors. With micro-sensor constantly expanding the scope of application of the sensor increasingly high demands of the future microsensor the main requirements are: miniaturization and integration of low-power and low-cost high-precision and long life; - and intelligent. Micromachined silicon integrated circuits and the integration of integration, to meet the above-mentioned requirements. At present, the majority of products integrated sensor using hybrid integrated, monolithic integration of a very small percentage. And the realization of single-chip integration is the key to achieving intelligent sensors, in particular monolithic integrated MEMS sensor technology is todays system-on-chip can achieve one of the key technologies. Clearly, monolithic integration of the various technical difficulties analysis of MEMS and have already given the various monolithic integration of MEMS technology is essential.在过去的20年中，CMOS技术已成为集成电路主要制造工艺，制造成本下降的同时，成品率和产量也得到很大提高，COMS工艺将继续以增加集成度和减小特制尺寸向前发展。当今，CMOS集成工艺不仅被利用在集成电路设计上，而且，也被利用在很多微传感器和微执行器上，这样可以把微传感器与集成电路集成在一起，构成功能强大的智能传感器。随着微传感应用范围的不断扩大，对传感器的要求也越来越高，对未来微传感器的主要要求是：微型化和集成化；低功耗和低成本；高精度和长寿命；多功能和智能化。硅微机械和集成电路的一体化集成，可以满足上述要求。目前，集成传感器的产品多数采用混合集成，单片集成的比例很小。而实现单片集成是实现传感器智能化的关键，特别是单片集成MEMS传感器技术也是当今片上系统芯片能否实现的关键技术之一。可见，对各种单片集成MEMS技术难点进行分析以及给出目前已有的各种单片集成MEMS技术是非常必要的。1.Monolithic integration of MEMS technology advantages and the challenges facing。1.单片集成MEMS技术的优势和面临的挑战MEMS and CMOS achieve working together, the separate manufacturing CMOS MEMS sensors and integrated circuits, and then cut from their chips, fixed in a common substrate, and, bonded connection, thereby bringing the two integration, This is the so-called mixed (hybrid) method. This method does not produce MEMS manufacturing process for CMOS circuits pollution At the same time, both the production process Noninterference. However, due to signal bonding point and fuses, resulting in high-frequency applications, decline in the quality of signal transmission, and to develop two production lines to increase the cost of the product. In order to address some performance issues, and lower manufacturing costs, and proposed to do in the part of MEMS and CMOS circuits with a substrate, which is produced compatible with CMOS technology or monolithic integrated MEMS technology called CMOS-MEMS technology. This method relative hybrid method generally have the following advantages: First, the performance can be greatly improved, because parasitic capacitance and crosstalk phenomenon can be significantly reduced; second, hybrid method requires sophisticated technology to reduce packaging Sensor Interface affected, and monolithic integration requires packaging technology is relatively simple and therefore, lower cost sensors; third, monolithic integrated sensor array sensor technology is the need to overcome the array sensor and external decoding circuit an effective interconnect bottleneck; Fourth, the development of monolithic integrated mixed development of MEMS products than MEMS products for a short time, and to develop low cost.实现MEMS和CMOS共同工作是分别制造MEMS传感器和CMOS集成电路，然后，从各自的晶片切开，固定在一个共同的衬底上，并且，连线键合，这样就实现两者的集成，这就是所谓的混合（hybrid）方法。这种方法不会产生MEMS制造过程对CMOS电路的污染，同时，两者生产过程互不干扰。但是，由于信号经过键合点和引线，导致在高频应用时，信号传输质量下降，并且，开发两套生产线增加了产品的成本。为了解决一些性能问题，并降低制造成本，提出把MEMS部分做在和CMOS电路同一块衬底上，也就是产生了与CMOS工艺兼容单片集成MEMS技术或叫CMOS-MEMS技术。这种方法相对混合方法总的来说有如下优势：第一，性能能得到很大的提高，因为寄生电容和串扰现象可以显著减小；第二，混合方法需要复杂的封装技术以减小传感器接口的影响，而单片集成方法需要的封装技术相对简单，所以，降低传感器成本；第三，单片集成传感器技术也是阵列传感器的需要，是克服阵列传感器与外围译码电路互连瓶颈的一种有效方法；第四，开发单片集成MEMS产品比开发混合MEMS产品所需的时间短，而且，开发成本低。Monolithic integration of MEMS technology under some of MEMS devices and CMOS circuit can be divided into different order processing before CMOS (pre-CMOS), mixed CMOS (intermediate-CMOS), and after the CMOS (post-CMOS) integrated approach.单片集成MEMS技术根据MEMS器件部分与CMOS电路部分加工顺序不同可以分为前CMOS（pre-CMOS）、混合CMOS（intermediate-CMOS）及后CMOS（post-CMOS）集成方法。Post-CMOS approach is in the processing of silicon CMOS circuits End, through some additional MEMS micro-processing technology to achieve monolithic integrated MEMS system, at present, monolithic integration of MEMS technology in this way mainly based. Post-CMOS approach is the main issue on MEMS processing temperature CMOS circuit performance in front of an impact on more serious is that the technology behind high-temperature MEMS processing temperature and metal CMOS process ahead of incompatibility. In the present study as the most polysilicon layer structure of the MEMS example, the densification of phosphorus glass annealing temperature is 950 due to a structural polysilicon layer of stress annealing temperature reached 1050 , which will enable CMOS devices junction depth migration occurred. In particular 800 shallow junction devices junction depth migration will affect device performance. On the other hand, the conventional aluminum metallization process, when the temperature reaches 400-450 , the reliability of CMOS circuits will be severely affected. From the above we can see that: how to overcome behind high-temperature MEMS processing temperature on the micro-structure of the front end processing has been the impact of CMOS circuits integrated MEMS single-chip solution is key to the system. At present, the international community is essential to resolve this issue through three ways: First is the interconnection of refractory metals instead of aluminum metal interconnect, for example, the University of Berkeley to replace tungsten aluminum metal interconnect programmes, such follow-up increased tolerance MEMS processing for high temperature; The second is produced by finding low temperature mechanical properties and excellent substitute materials as structural polysilicon layer; third way is to use its existing structure CMOS MEMS layer as a layer structure.post-CMOS方法是在加工完CMOS电路的硅片上，通过一些附加MEMS微细加工技术以实现单片集成MEMS系统，目前，单片集成MEMS技术主要以这种方法为主。post-CMOS方法主要问题是MEMS加工工艺温度会对前面的CMOS电路性能产生影响，更为严重的是后面高温MEMS加工工艺温度与前面CMOS工艺金属化不兼容。以目前研究最多的多晶硅作为结构层的MEMS为例，使磷硅玻璃致密化退火温度为950，而使作为结构层多晶硅的应力退火温度则达到1050，这将使CMOS器件结深发生迁移。特别是800时浅结器件的结深迁移就会影响器件的性能。另一方面，采用常规铝金属化工艺时，当温度达到400-450时，CMOS电路可靠性将受到严重的影响。从以上可以看出：如何克服后面高温MEMS微结构加工温度对前面的已加工完的CMOS电路影响是解决单片集成MEMS系统关键所在。目前，国际上解决这个问题基本是通过3种方式：第一种是以难熔金属化互连代替铝金属化互连，如，伯克利大学的以钨代替铝金属互连方案，这样提高容忍后续加工MEMS所需的高温；第二种方式是通过寻找低制作温度且机械性能优良的材料代替多晶硅作为结构层材料；第三种方式是利用CMOS本身已有结构层作为MEMS结构层。Pre-CMOS integrated approach is to create structure MEMS manufacturing CMOS circuits, although this integrated CMOS technology to overcome post-CMOS method of high-temperature MEMS Technology on CMOS circuits affected, but because of the existence of micro-vertical structure, and therefore, there sensor and circuit interconnection level coverage, but also in the process of CMOS circuits on the micro-structure protection is also a need to consider the issue. Even fine-tune the optimization of CMOS process, such as: gate oxide may be heavily doped layer impact of the structure. In addition, the MEMS technology can not process any of the metal or other materials, such as piezoelectric polymers, and so on, makes this method only suitable for some special applications.pre-CMOS集成方法是先制造MEMS结构后制造CMOS电路，这种集成CMOS技术虽然克服post-CMOS方法中MEMS高温工艺对CMOS电路的影响，但由于存在垂直的微结构，所以，存在传感器与电路互连台阶覆盖性问题，而且，在CMOS电路工艺过程中对微结构的保护也是一个需要考虑的问题。甚至已优化微调的CMOS工艺流程，例如：栅氧化可能被重掺杂的结构层影响。另外，MEMS工艺过程中不能有任何的金属或其他的材料，如压电材料聚合物等，使得这种方法只适合一些特殊应用。Intermediate-CMOS circuits in the CMOS production process to insert some MEMS micro-processing technology to achieve monolithic integrated MEMS approach. This approach has been very mature and have a lot of commercialization of products, is the first study of a single-chip integration method is to solve the pre - and post-CMOS CMOS method effective method problems, but due to the need for the existing standard CMOS or larger BiCMOS process changes, therefore, the use of this method is ermediate-CMOS是在CMOS电路生产过程中插入一些MEMS微细加工工艺来实现单片集成MEMS的方法。这种方法已很成熟，并已有很多商品化产品，也是研究最早一种单片集成方法，是解决pre-CMOS和post-CMOS方法存在问题有效方法，但是，由于需要对现有的标准CMOS或BiCMOS工艺进行较大的修改，因此，这种方法的使用有一定限制。1.The main monolithic integrated MEMS technology status单片集成MEMS的主要技术现状At present, the monolithic integration of MEMS technology mainly to post-CMOS technologies, through a series of compatible with CMOS process on the surface micro-machining and processing to achieve monolithic integration of MEMS. Can be divided into two kinds: one is in the top layer CMOS structure to a structure layer deposition micro-machining; the other is directly CMOS layer structure as the original structure of the MEMS micro-machined.目前，单片集成MEMS技术主要以post-CMOS技术为主，通过一系列的与CMOS工艺兼容的表面微细加工和体加工实现单片集成MEMS。又可分为2种：一种是在CMOS结构层上面再淀积一层结构层的微加工；另一种是直接以CMOS原有的结构层作为MEMS结构层的微加工。2.1Deposition of new structural materials for the structure of integrated MEMS technology2.1淀积新的结构材料作MEMS结构的集成技术2.1.1Polysilicon layer structure as the surface micro-machining technology integration2.1.1多晶硅作为结构层的集成表面微细加工技术This process is typical of modules developed at the University of Berkeley Integrated CMOS and MEMS Technology (modular integration of CMOS with micro-structures, MICS), this method is for the micro-structural polysilicon layer, phosphorus silicon glass (PSG) as a sacrificial layer The surface micro-machining technology. A refractory metal tungsten metal interconnect instead of aluminum metal interconnect to bear behind the polysilicon production needs of micro-structure of high-temperature, but at 600 , tungsten and silicon form easily response by the University of Berkeley in the Contacts release a TiN barrier layer to address this problem. MICS process is the basic process: the completion of tungsten metal CMOS process, the deposition of 300 10-10nm low-temperature oxide (LTO), and then, low pressure chemical vapor deposition 200 10-10nm protection of the silicon nitride film has been produced CMOS circuits, micro-structure and corrosion End CMOS circuit contact hole, No. 1 layer deposition scene doped polysilicon (350 10-10), as CMOS circuits and micro-structure of interconnection lines, in the above deposition to a um PSG thick as a sacrificial layer thickness and deposition of 2 um polysilicon layer structure. No. 2 through another layer polysilicon deposition of a layer of 0.5 um PSG, as well as nitrogen environment in the 1000 rapid thermal annealing for 1 min as a structure to reduce stress polysilicon layer. Finally, the structure of graphics and polysilicon etching out its corrosion layer below the sacrifices (PSG) for the release of micro-structure.这种工艺典型代表是伯克利大学开发模块集成CMOS与MEMS工艺（modular integration of CMOS with micro-structures，MICS），这种方法是以多晶硅为微结构层，磷硅玻璃（PSG）作为牺牲层的表面微细加工技术。采用难熔金属钨的金属化互连代替铝金属化互连以承受后面的生产多晶硅微结构所需要的高温，但是，在600时，钨容易与硅形成反应，伯克利大学是通过在接触孔上放一层TiN阻挡层来解决这一问题的。MICS工艺基本流程是：完成钨金属化的CMOS工艺后，淀积30010-10nm低温氧化物（LTO），然后，低压化学气相淀积20010-10nm的氮化硅薄膜保护已生产的CMOS电路，腐蚀完微结构与CMOS电路的接触孔后，淀积第1层现场掺杂多晶硅（35010-10）作为CMOS电路与微结构的互连线，再在上面淀积1um厚的PSG作为牺牲层以及淀积厚度为2um多晶硅结构层。通过在第2层多晶硅上再淀积一层0.5um的PSG，以及在氮气环境下的1000快速退火1min来降低作为结构层的多晶硅应力。最后，刻蚀多晶硅结构图形以及腐蚀掉其下面的牺牲层（PSG）以释放微结构。2.1.2Other materials for the structure of the surface micro-machining technology integration2.1.2以其他材料作结构层集成表面微细加工技术Polycrystalline silicon germanium polysilicon not only with the excellent mechanical properties similar, and, low temperature deposition compatible with the CMOS process, therefore, is being extensively studied. Developed at the University of Berkeley-based structural layer of silicon germanium technology and MICS technology similar. Major technological innovations: First, the protective layer using different materials, before 835 MICS process is the LPCVD silicon nitride, and now it is using a two-tier LTO and intermediate folder is not a stereotypical silicon (a-Si) as a CMOS circuit protective layer, in which the two-step deposition of a-Si, the first step in the deposition 450 ; step deposition in the 410 , this will not damage the temperature of aluminum metal CMOS circuit; Second, the low amylin plot structure as a temperature polysilicon layer of germanium materials, the low pressure chemical vapor deposition (LPCVD) temperature only 400 using rapid thermal annealing temperature of only 5.5 for 30 s. MICS and the temperature polysilicon deposition of more than 600 . From the above two points, we can see that the whole follow-up MEMS processing temperature does not exceed 450 , therefore, not of aluminum metal interconnect CMOS circuits have greatly affected.多晶硅锗不仅有与多晶硅相似的优良机械性能，而且，淀积温度低与CMOS工艺兼容，所以，目前被广泛研究。伯克利大学开发的基于硅锗结构层的工艺与MICS工艺基本相似。主要技术革新：第一，保护层采用不同的材料，以前MICS工艺采用835的LPCVD氮化硅，而现在则是采用两层LTO和中间夹一层不定型硅（a-Si）作为CMOS电路保护层，其中，a-Si分两步淀积，第一步淀积在450；第二步淀积则在410，这样温度是不会损坏铝金属化CMOS电路；第二，采用低淀积温度多晶硅锗作为结构层材料，其低压化学气相淀积（LPCVD）温度只有400，采用快速退火温度也仅为550，时间为30s。而MICS工艺淀积多晶硅结构温度则超过600。从以上两点可知，由于整个后续MEMS加工温度不超过450，所以，不会对铝金属化互连CMOS电路产生很大的影响。Aluminum used as a structural material will be a great success, the most successful is the Texas Instruments developed cryogenic surface micro-machining technology, and use this technology successfully produced digital micromirror device (DMD). Technical innovation in the use of sputtering performance as aluminum structural material, and using photoresist as a sacrificial layer, which makes low-temperature post-processing production has been below the SRAM cells were not damaged.采用铝作为结构层材料也会获得很大成功，最为成功的是德州仪器开发低温表面微细加工技术，并用这种技术成功生产了数字微镜设备（DMD）。技术革新主要表现在采用溅射铝作为结构层材料，并且，采用光致抗蚀剂作为牺牲层，这种低温后处理使得已生产的下面SRAM单元不被破坏 。Lead zirconate titanate (PZT) of the material has an excellent result piezoelectric properties, pyroelectric properties of ferroelectric properties and dielectric properties and is widely used in ferroelectric memory, as well as high-dielectric materials. At the same time, we can also use lead zirconate titanate piezoelectric effect produced micro-sensors and micro-actuators. PZT thin film silicon technology and integration technology compatible, such as the present based on the metal-organic chemical vapor deposition (OCVD) Methods PZT thin films temperature has been reduced to 430 to 75 , the temperature is lower, therefore, use of such materials as structural layer is a very hopeful and CMOS process integration.锆钛酸铅（PZT）电材料因具有优良的压电性能、热释电性能、铁电性能和介电性能而被广泛应用在铁电存储器中以及作为高介质材料。同时，还可以利用锆钛酸铅压电效应制作微传感器以及微执行器。PZT薄膜工艺与硅集成工艺兼容，如，目前的基于金属有机化学气相淀积（OCVD）方法制作PZT薄膜温度已降低到43075，这个温度还在降低，因此，采用这种材料作为结构层是很有希望与CMOS工艺集成的。2.2 CMOS structure to the original layer to the structure of integrated MEMS technology2.2以原CMOS结构层作MEMS结构的集成技术2.2.1Sacrifice aluminum micro-machining technology2.2.1牺牲铝的微加工技术If CMOS metal compounds used for the expense of materials, there may be fully compatible with CMOS technology and surface micro-machining small art, this method is called sacrifice aluminum etching (sacrificial aluminum etching, SALE). In many CMOS process, use two layers of aluminum alloy by a metal layer. No. 1 as a sacrificial layer of metal was removed, can create metal dielectric compounds; Layer 2 and passivation of the metal component, 2-layer metal between two dielectric between appropriate structure, they could serve as a mirror electrodes, heat or electric resistance regulator. The basic process include: (1) the protection of electrical contacts are not connected etching (2) corrosion sacrifice aluminum layer; (3) removal rinsed Boundary structure inside the etching agent; (4)-drying bodies.如果CMOS金属化合物用作牺牲材料，则可能存在和CMOS工艺完全兼容的表面微细加工丁艺，这种方法被称作牺牲铝蚀刻（sacrificial aluminum etching，SALE）。在许多CMOS工艺过程中，都采用了两层由铝合金构成的金属层。第1层金属作为牺牲层被清除，可以制造出电介质金属化合物；第2层由金属和钝化物组成，第2层金属介于两个电介质之间，适当结构化后，便可以作为反射镜、电极、热电阻或电热调节器。其基本工艺过程包括：（1）保护电气连接触点不受到蚀刻；（2）腐蚀牺牲铝层；（3）涮洗清除徼结构里面的蚀刻剂；（4）烘干微机构。2.2.2Monocrystal silicon etching and metal activation method.2.2.2单晶体硅活化蚀刻和金属化法Monomer silicon etching and metal activation method (single crystal reactiveetching and metallization, SCREAM) can be used for manufacturing, beam, the bridge structure, and even silicon can be used to create more complex structures. This approach starts at the End manufacture silicon CMOS circuits, first of all, a layer of coverage deposition contact hole silicon oxide, oxide layer to protect it from the back of CMOS circuits affected, and through reactive ion etching (RIE) of this graphics Oxide layer shielding layer; then RIE etching silicon trench, the depth of up to 10 um, silicon oxide thin film deposition down, and the level of coverage in the side surface. By reactive ion etching of the oxide surface level off due to a vertical surface to be protected, the second reactive ion etching silicon; Finally, the isotropic etch silicon, the release of the microstructure of a suspension, at the same time, etching contact hole oxides, and Sputtering metal, this layer of metal deposition to the aspect ratio of the beam into a capacitive elements with thick resist masking agent for the graphics mode of metal layers. As each step of SCREAM are below 300 under the temperature and, therefore, is compatible with CMOS circuits.单体硅活化蚀刻和金属化法（single crystal reactiveetching and metallization，SCREAM）可用于制造，梁、桥这样的结构，甚至可以用单晶硅制造更复杂的结构。这种方法始于制造完的CMOS电路硅片，首先，淀积一层覆盖接触孔的氧化硅，这层氧化物保护CMOS电路免受后面工艺影响，并通过反应离子蚀刻（RIE）图形化这层氧化物遮蔽层；然后，RIE蚀刻硅沟槽，深度可达到10um，氧化硅薄膜淀积下来，覆盖在侧面和水平面上。通过反应离子蚀刻掉水平面上的氧化物，而使竖直面受到保护，第二次反应离子蚀刻硅；最后，各向同性蚀刻硅，释放出悬浮的微结构，同时，蚀刻接触孔氧化物，并溅射金属，这层金属化淀积物使大纵横比的粱变成电容性元素，用厚的抗蚀剂作掩蔽模图形化金属层。由于SCREAM的每一步均在低于300的温度下进行的，因此，是与CMOS电路兼容的。2.2.3Large aspect ratio of CMOS-MEMS Technology2.2.3大纵横比的CMOS-MEMS工艺Gamegle Melloa University and the development of CMOS-compatible dry etching method, which isotropic silicon etch applications have insulation film, CMOS dielectric and metal layers in this process, not only for the metal interconnect, but also as a micro-mechanical structure tail. Basic process: First, the standard CMOS process using three-metal process to achieve 0.5 upmN Well, secondly, metal layers 1 and 2 were used as electrical activity layer, and layer 3 as a micro-machining etching mask. Application of the compound CHF3/O2 reactive ion etching (RIE), the entire chip passivation layer to be removed, in the three-tier regional disconnect metal, CMOS laminated film has been etched to the basement, and above covered with Layer 3 CMOS metal thin film laminated retained intact; Finally, the use of SP6/O2 plasma etching in the micro-structural wall not under isotropic etch silicon substrate. Narrow insulating layer and conductive layer fused to create beams and bridges, such as: Comb drive the micro-structure.Gamegle Melloa大学开发的与CMOS兼容干法蚀刻方法，它应用各向同性硅蚀刻产生绝缘薄膜，CMOS介质和金属化层在这个工艺中不仅用作金属互连，而且，还作为微机械结构尾。基本工艺过程为：首先，标准的CMOS工艺采用三层金属0.5upmN阱工艺实现；其次，金属层1和2被用作电活性层，而第3层作为微机械加工的蚀刻掩模。应用化合物CHF3O2的反应离子蚀刻（RIE），使整个芯片上的钝化层被清除掉，在第3层金属断开区域，CMOS薄膜夹层被一直蚀刻至基底，而上面覆盖有第3层金属的CMOS薄膜夹层则保留完好；最后，采用SP6O2等离子在不蚀刻微结构侧壁情况下各向同性蚀刻硅衬底。狭窄的绝缘层和导电层融为一体制造出梁和桥，例如：梳状驱动器这样的微结构。2.2.4 Processing CMOS-MEMS Technology2.2.4体加工CMOS-MEMS工艺Mainly through the etching of silicon substrates, such as processing technology to form the necessary MEMS structure, the technology mainly to the University of Zurich-based. Can be viewed in a positive etching silicon substrate, but also from negative etching silicon substrate, using anisotropic etching (100) in the direction of the characteristics of the silicon etching could be positive not closed micro-structure, such as beams and support film , the choice of etching can be tetramethyl ammonium hydroxide solution (TMATH) or ethylene diamine solution (EDP). From what has been done through the back of the silicon wafer of silicon can be pitting the closure of the dielectric film, the need for a definition of additional patch mask the size of the commonly used candle is engraved on KOH. 主要是通过蚀刻硅衬底等体加工技术来形成所需的MEMS结构，这种技术主要以苏黎世大学为主。可以从正面蚀刻硅衬底，也可以从反面蚀刻硅衬底，利用各向异性腐蚀（100）方向的特性，从硅的正面蚀刻是可以得到未封闭的微结构，如，梁和支撑膜等，可选用的蚀刻剂可以是氢氧化四甲基铵水溶液（TMATH）或乙烯二胺溶液（EDP）。通过从已完成的硅片背部蚀该硅片可以得到封闭的介电薄膜，需要一个额外的掩模定义膜片的大小，通常采用的烛刻剂是KOH。 XeF2 dry etching using the post-CMOS technology has also made great development. XeP2 is an anisotropic etching of silicon, etching at high velocity, it is an inert gas xenon rare compounds. XeP2 neither IC insulating layer etching, etching aluminum or metal compounds, therefore, and CMOS compatible. After the appropriate regional design, connectivity and processing mask, opened in designated parts insulating layer, so that local exposure to silicon substrate etching agent. XeF2 because that is not etched ceramic, not plastic etching and thus suitable for CMOS integrated micro-processing system. In the use of this method can be completed with CMOS chip micro-etching mask institutions.采用XeF2干法蚀刻的post-CMOS工艺也得到很大的发展。XeP2是一种各向异性硅蚀刻剂，蚀刻速度很高，它是惰性气体氙的一种稀有化合物。XeP2既不蚀刻IC绝缘层，也不蚀刻铝合金金属化合物，因此，和CMOS完全兼容。经过适当的区域设计、连接和加掩模，在指定部位打开绝缘层，使基底硅局部暴露给蚀刻剂。因为XeF2即不蚀刻陶瓷，也不蚀刻塑料，从而适合集成CMOS微系统的微加工。使用这种方法可在已完成的CMOS芯片上无掩模蚀刻出微机构。3.Development Trend 3.发展趋势Monolithically integrated MEMS technology has been developing for more than 10 years, has been the rapid development has also seen the emergence of a MEMS manufacturing services organizations and enterprises, which will be some special organizations or directly from the IC manufacturers to provide MEMS processing. IC Microsystems representative of the direction of technology development organizations, including the United States and Europe TIMACMP MOSIS.Europractice; North Kaluona state Croons Integrated Microsystems Inc., in addition to providing the basic CMOS process, the body also provides micro-machining and surface emblem processing, LIGA process, as well as multi-user MEMS technology; the United States Sandia National Laboratory d
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