AT89S51单片机.doc

The Description of AT89S511 General DescriptionThe AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.2 PortsPort 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the fol-lowing table.3 Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea-tures. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.4 Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.4.1 Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.4.2 Data MemoryThe AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. 7. Watchdog Timer (One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.5 Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the AT89C51. 6 InterruptsThe AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 10-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that Table 10-1 shows that bit positions IE.6 and IE.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.7 Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 11-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.8 Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.Power-down ModeIn the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. AT89S51概述1 一般概述 该AT89S51是一个低功耗，高性能CMOS 8位微控制器,可在4K字节的系统内编程的闪存存储器。该设备是采用Atmel的高密度非易失性存储器技术和符合工业标准的80C51指令集和引脚。芯片上的Flash程序存储器可重新编程的系统或常规非易失性内存编程 。通过结合通用8位中央处理器的系统内可编程闪存的单芯片， AT89S51是一个功能强大的微控制器提供了高度灵活的和具有成本效益的解决办法，可在许多嵌入式控制中应用。 在AT89S51提供以下标准功能： 4K字节的Flash闪存 ， 128字节的RAM ， 32个 I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器， 5向量两级中断结构，全双工串行端口，片上振荡器和时钟电路。此外， AT89S51设计的静态逻辑操作到零频率和支持两种软件可选节电模式。空闲模式停止的CPU ，同时允许的RAM ，定时器/计数器，串行接口和中断系统继续运作。在掉电模式保存RAM内容，可停止振荡器，停用所有其他芯片的功能，直到下一个外部中断或硬件复位。 2 端口端口0是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可汇8的TTL输入。当1写入端口0引脚，该引脚可作为高阻抗输入。端口0也可以配置为复低阶地址/数据总线，在访问外部程序和数据存储器。在这种模式下， P0了内部无上拉。端口还收到0字节的代码在Flash编程和产出代码波特率的核查。外部上拉需要在使用。 端口1是一个8位双向I / O端口内部上拉。端口1输出缓冲器可以驱动四个TTL。当1写入端口1引脚，他们的退出高足态上拉，可作为输入。作为输入，端口1引脚的外部被拉低将电源电流（ IIL ）由于内部上拉。端口1还收到低字节为了解决在Flash编程和核查。 端口2是一个8位双向I / O端口内部上拉。端口2输出缓冲器可以驱动四的TTL输入。当1写入端口2，他们的退出高阻态上拉，可作为输入。作为输入，端口2引脚的外部被拉低将电源电流（ IIL ）由于内部上拉。端口2排放高阶地址字节在获取外部程序存储器和杜尔法访问外部数据存储器，使用16位地址（ MOVX DPTR ） 。在此应用程序，端口2使用强大的内部上拉时，发射谱。在访问外部数据存储器，使用8位地址（ MOVX 里） ，端口2发出的内容， P2的特殊功能寄存器。端口2还收到高阶地址位和一些控制信号在闪存程序明和核查。 端口3是8位双向I / O端口内部上拉。端口3输出缓冲器可以驱动四个TTL输入。当1写入端口3引脚，他们的退出高阻态上拉，可作为输入。作为输入，端口3引脚的外部被拉低将电源电流（ IIL ）因为上拉。端口3获得某种程度的控制信号的Flash编程和核查。端口3兼任的职能。 3 特殊功能寄存器 片上存储器区域称为特殊功能寄存器（ SFR的）。请注意，并非所有的地址都被占领，未使用的的地址可以寻址。阅读访问这些地址将一般返回随机数据，写访问将有不确定的结果。 用户软件不应该写入对这些非寻址地址。在这种情况下，重置值或无效的新的双向数据将永远是0 。中断寄存器：个人中断启用BITS是在IE注册。两个优先级可以设定为每一个中断源的优先顺序。双数据指针寄存器：为了便于访问内部和外部数据存储器，这两家指针的16位数据指针寄存器提供： DP0地点在SFR的地址82H - 83H和DP1在84H - 85H 。位的DPS = 0中的SFR选择DP0和AUXR1的DPS = 1选择DP1 。 用户应始终初始化的DPS位到适当的值之前，各自的数据存取指针寄存器。 断电检举：电源（光纤）位于位4 （ PCON.4 ）在PCON SFR。它可以设置和其他软件的控制下，是不会受到影响复位。 4 存储设备 MCS - 51单片机的设备有一个单独地址空间的程序和数据存储器。高达64K字节的外部程序和数据存储器可以得到解决。4.1 程序存储器 如果的EA引脚连接到GND ，获取所有程序都是针对外部存储器。关于AT89S51 ，如果EA连接到VCC ，计划获取地址0000H通过FFFH是针对内部存储器和存取的地址1000H通过FFFFH是针对外部存储器。4.2 数据存储器 AT89S51实施的128字节的片上RAM 。 128字节都可以通过直接和间接寻址模式。栈操作的例子间接寻址，因此， 128字节的数据RAM可作为堆栈空间。5 定时器 看门狗定时器（一次性启用了复位输出）的定时器是作为恢复方法的情况下的CPU可能会受到软件冷门。该定时器包括一个14位计数器和看门狗定时器复位（ WDTRST ） SFR公司。该定时器是拖欠禁用从朝重置。为了使定时器，用户必须写入01EH和0E1H依次向WDTRST寄存器（ SFR的位置0A6H ） 。当定时器启用，它会增加，而每个机器周期振荡器正在运行。该定时器超时时间依赖于外部时钟频率。没有办法禁用定时器除了通过重置（或者硬件复位或定时器溢出复位） 。当定时器过度流动，将驱动器输出复位高脉冲的复位引脚。为了使定时器，用户必须写入01EH和0E1H顺序登记的WDTRST（ SFR的位置0A6H ） 。当定时器被激活，用户需要的服务以书面01EH和0E1H到WDTRST以避免定时器溢出。 14位计数器溢出时，达到16383 （ 3FFFH ）