第四章逻辑门电路作业题(参考答案)

1、第四章 逻辑门电路（Logic Gates Circuits）1知识要点CMOS逻辑电平和噪声容限；CMOS逻辑反相器、与非门、或非门、非反相门、与或非门电路的结构；CMOS逻辑电路的稳态电气特性：带电阻性负载的电路特性、非理想输入时的电路特性、负载效应、不用的输入端及等效的输入/输出电路模型；动态电气特性：转换时间、传输延迟、电流尖峰、扇出特性；特殊的输入/输出电路结构：CMOS传输门、三态输出结构、施密特触发器输入结构、漏极开路输出结构。重点：1CMOS逻辑门电路的结构特点及与逻辑表达式的对应关系；2CMOS逻辑电平的定义和噪声容限的计算；3逻辑门电路扇出的定义及计算；4逻辑门电路转换时间

2、、传输延迟的定义。难点：1CMOS互补网络结构的分析和设计；2逻辑门电路对负载的驱动能力的计算。（1）PMOS和NMOS场效应管的开关特性MOSFET管实际上由4部分组成：Gate，Source，Drain和Backgate，Source和Drain之间由Backgate连接，当Gate对Backgate的电压超过某个值时，Source和Drain之间的电介质就会形成一个通道，使得两者之间产生电流，从而导通管子，这个电压值称为阈值电压。对PMOS管而言，阈值电压是负值，而对NMOS管而言，阈值电压是正值。也就是说，在逻辑电路中，NMOS管和PMOS管均可看做受控开关，对于高电平1，NMOS导通

3、，PMOS截断 ；对于低电平0，NMOS截断，PMOS导通。（2）CMOS门电路的构成规律每个CMOS门电路都由NMOS电路和PMOS电路两部分组成，并且每个输入都同时加到一个NMOS管和一个PMOS管的栅极（Gate）上。对正逻辑约定而言，NMOS管的串联（Series Connection）可实现与操作（Implement AND Operation），并联（Parallel Connection）可实现或操作（Implement OR Operation）。PMOS电路与NMOS电路呈对偶关系，即当NMOS管串联时，其相应的PMOS管一定是并联的；而当NMOS管并联时，其相应的PMOS管

4、一定需要串联。基本逻辑关系体现在NMOS管的网络上，由于NMOS网络接地，输出需要反相（取非）。（3）CMOS逻辑电路的稳态电气特性 一般来说，器件参数表中用以下参数来说明器件的逻辑电平定义：VOHmin 输出为高电平时的最小输出电压VIHmin 能保证被识别为高电平时的最小输入电压VOLmax 能保证被识别为低电平时的最大输入电压VILmax 输出为低电平时的最大输出电压不同逻辑种类对应的参数值不同。输入电压主要由晶体管的开关门限电压决定，而输出电压主要由晶体管的“导通”电阻决定。噪声容限是指芯片在最坏输出电压情况下，多大的噪声电平会使得输出电压被破坏成不可识别的输入值。对于输出是高电平的情

5、况，其最坏的输出电压是VOHmin，如果要使该电压能在输入端被正确识别为高电平，即被噪声污染后的电压值应该不小于VIHmin，则噪声容限为VOHmin-VIHmin。对于输出是低电平的情况，噪声容限为VILmax -VOLmax。输出电流的定义如下。IOLmax：输出低态且仍能维持输出电压不大于VOLmax时，输出端能吸收的最大电流；IOHmax：输出高态且仍能维持输出电压不小于VOHmin时，输出端可提供的最大电流。（4）扇出逻辑门的扇出（fanout）是指该门电路在不超出其最坏情况负载规格的条件下能驱动的输入端的个数。扇出不仅依赖于输出端的特性，还依赖于它驱动的输入端的特性。扇出的计算必须

6、考虑输出的两种可能状态：高电平状态和低电平状态。直流扇出能力的计算方法为：最大输出电流/最大输入电流。一个门电路的高电平扇出和低电平扇出不一定相等。通常，门电路的总扇出应为高电平扇出和低电平扇出中的较小值。（5）CMOS电路的动态特性转换时间可分为输出上升时间tr和输出下降时间tf，其值的大小和门的导通电阻与负载电容之积成正比。传输延迟时间tp指的是从输入变化到输出变化所需的时间。其值取决于器件内部的结构与信号传输的路径；同一个器件，不同输入/输出间的传输延迟可能不同，由多种因素决定。（6）CMOS电路的功耗输出不变时的CMOS电路功耗称为静态功耗。CMOS电路在状态转换时消耗的电能称为动态功

7、耗，其来源是输出端上的电容性负载CL，输出从低到高转换时，电流流过P沟道晶体管给负载充电，类似地，输出从高到低转换时，电流流过N沟道晶体管给负载放电，这两种情况下晶体管导通的电阻都消耗功率。充电开始时电压变化为VDD，结束时电压变化很小，故平均电压变化为VDD/2，则每次转换消耗的电能为，若每秒钟变化2f次，则由电容性负载引起的动态功耗为。2Exercises 4.1 The Stub Series Terminalted low Voltage(SSTV) logic family, used for SDRAM modules, defines a LOW signal to be in

8、the range 0.00.7V, and a HIGH signal to be in the range 1.72.5V. Under a positive-logic convention, indicate the logic value associated with each of the following signal levels:(a) 0.0V(b) 0.7V(c) 1.7V(d) -0.6V (e) 1.6V(f) -2.0V(g) 2.5V(h) 3.3V(a) 0(b) 0(c) 1(d) undefined (e) undefined(f) undefined(

9、g) 1(h) undefined4.2 Repeat exercise 4.1 using a negative-logic convention.(a) 1(b) 1(c) 0(d) undefined(e) undefined(f) undefined(g) 0(h) undefined4.3 True or false: For a given set of input values, a NAND gate produces the opposite output as a NOR gate.When the two inputs are different, it will be

10、ture.4.4 For a given silicon area, which is likely to be faster, a CMOS NAND gate or a CMOS NOR?CMOS NAND will be faster than CMOS NOR.4.5 Which has fewer transistors, a CMOS inverting gate or a noninverting gate?CMOS inverting gate has fewer transistors.4.6 For each of the following resistive loads

11、, determine whether the output drive specifications of the 74HC00 over the commercial operating range are exceeded (use V= 0.33V，VOHmin = 3.84V and VCC = 5.0 V). You may not exceed IOLmax (4mA) or IOHmax (4mA) in any state.(1) 1.2k W to VCC and 820 W to GND(2) 470 W to VCC and 470 W to GND74HC00VccV

12、cc1.2k W820 WVoVin1Vin2R1R2(1) VThev = Vcc×R2 / (R1+R2) = 5×820 / (1200+820) 2.03VI Short = Vcc / R1RThev = VThev / I Short= R1×R2 / (R1+R2)= 1200×820 / (1200+820) 487.13 WVOHmin = 3.84V IOH = (VOHmin-VThev ) / RThev 3.7 mA < IOHmax = 4 mAVOLmax = 0.33V IOL = (VThev - VOLmax)

13、/ RThev 3.5 mA < IOLmax = 4 mA因此，没有超出商用工作范围，可以正常驱动负载。74HC00VccVcc270330VoVin1Vin2R1R274HC00VccVcc470 W470 WVoVin1Vin2R1R2(2) VThev = Vcc×R2 / (R1+R2) = 5 / 2= 2.5VI Short = Vcc / R1RThev = VThev / I Short= R1×R2 / (R1+R2)= 470 / 2= 235 WVOHmin = 3.84V IOH = (VOHmin-VThev ) / RThev 5.7 m

14、A > IOHmax = 4 mAVOLmax = 0.33V IOL = (VThev - VOLmax) / RThev 9.2 mA > IOLmax = 4 mA因此，超出了商用工作范围，不能驱动负载。4.7 A particular Schmitt-trigger inverter has = 0.8 V, = 2.0 V, =1.7 V, and = 1.2 V. How much hysteresis does it have? Hysteresis = -= 1.7-1.2 = 0.5V4.8 Discuss the pros and cons of larger

15、versus smaller pull-up resistors for open-drain CMOS outputs.较小的上拉电阻：优点是输出电平在上升时较快，使得其工作运行的速度较快；缺点是在输出低电平时电源对地的电流较大，使得其功耗较大。较大的上拉电阻：优点是在输出低电平时电源对地的电流较小，使得其功耗较小；缺点是输出电平在上升时较慢，使得其工作运行的速度较慢。4.9 How many diodes are required for an n-input diode AND gate?n diodes are required.4.10 Compute the maximum fan

16、out for each of the following cases of a TTL output driving multiple TTL inputs. Also indicate how much “excess” driving capability is available in the LOW or HIGH state for each case. ( Refer to datasheets in Appendix )(1) 74LS driving 74AS (2) 74LS driving 74F (1) 根据数据表，74LS的IOLmax = 8 mA，74AS的IIL

17、max = -0.5 mA Low-state Fan-Out = 8 / 0.5 = 1674LS的IOHmax = -400A，74AS的IIHmax = 20A High-state Fan-Out = 400 / 20 = 20因此，总的最大扇出为16。高态剩余驱动能力 = (20-16)×20 = 80A(b) 根据数据表，74LS的IOLmax = 8 mA，74F的IILmax = -0.6 mA Low-state Fan-Out = 8 / 0.6 1374LS的IOHmax = -400A，74F的IIHmax = 20A High-state Fan-Out =

18、 400 / 20 = 20因此，总的最大扇出为13。高态剩余驱动能力 = (20-13)×20 = 140A4.11 Compute the LOW-state and HIGH-state DC noise margins for each of the following cases of a TTL-compatible CMOS output driving a TTL input, or vice versa. ( Refer to datasheets in Appendix )(1) 74HCT driving 74LS(2) 74ALS driving 74HCT(

19、1) 根据数据表，74HCT的VOHminT = 3.84V，74LS的VIHmin = 2.0V High-state Noise Margin : 3.84 2.0 = 1.84V74HCT的VOLmaxT = 0.33V，74LS的VILmax = 0.8V Low-state Noise Margin : 0.8 0.33 = 0.47V(2) 根据数据表，74ALS的VOHmin = 2.7V，74HCT的VIHmin = 2.0V High-state Noise Margin : 2.7 2.0 = 0.7V74ALS的VOLmax = 0.5V，74HCT的VILmax = 0

20、.8V Low-state Noise Margin : 0.8 0.5 = 0.3V4.12 Compute the maximum fanout for each of the following case of a TTL-compatible CMOS output driving multiple inputs in a TTL logic family. Also indicate how much “excess” driving capability is available in the LOW or HIGH state for each case. ( Refer to

21、datasheets in Appendix )(1) 74HCT driving 74LS(2) 74AHCT driving 74S(1) 根据数据表，74HCT的IOLmaxT = 4 mA，74LS的IILmax = -0.4 mA Low-state Fan-Out = 4 / 0.4 = 1074HCT的IOHmaxT = -4 mA，74LS的IIHmax = 20A High-state Fan-Out = 4000 / 20 = 200因此，总的最大扇出为10。高态剩余(excess)驱动能力 = (200-10)×20 = 3.8 mA(2) 根据数据表，74AH

22、CT的IOLmaxT = 8 mA，74S的IILmax = -2.0 mA Low-state Fan-Out = 8 / 2 = 474AHCT的IOHmaxT = -8 mA，74S的IIHmax = 50A High-state Fan-Out = 8000 / 50 = 160因此，总的最大扇出为4。高态剩余(excess)驱动能力 = (160-4)×50 = 7.8 mAOptions4.13 Draw a circuit diagram, function table, and logic symbol for a CMOS gate with two inputs A and B and an output Z, where Z = 1 if A = 0 and B = 1, and Z = 0 otherwise (Hint: Only six transistors are required).Fill out the truth table fist:A BZ0 000 111 001 10Get the logic expression: Z = A · B Then draw th