基于FPGA的通用信号处理模块设计与实现

摘要I摘要近年来，以 FPGA 为代表的可编程逻辑器件取得了快速的发展，FPGA 不仅解决了雷达信号处理机小型化、低功耗、高可靠性等问题，而且基于 FPGA 为核心的信号处理模块以其灵活的设计方式使其越来越多地取代 ASIC 的市场地位。FPGA 是一种半定制的集成电路，设计者可以完全控制设计的实现过程，不需要任何实际的集成电路制造设备。尽管以 DSP 作为处理核心的雷达信号处理机已经得到广泛应用，但它的缺点是实时性不好，FPGA 可以较好地解决这一问题。并且现在 FPGA 发展迅速，多数已经集成 DSP 处理模块。因此，FPGA 作为通用信号处理模块的核心具有很强的可操作性。基于雷达信号处理的要求，作者设计和完成了一个基于 FPGA 为核心的通用信号处理模块。该模块以一片大容量的 FPGA 作为信号处理的核心，使用 SDRAM 和FLASH 进行外部数据存储，单片机作为 FPGA 和计算机的中介桥梁，通过串口在计算机上对模块进行非实时调试和监控。为了完成本课题，本文在以下几个方面进行研究：首先对雷达信号处理的特点进行了详细的分析，得出脉冲压缩、MTI/MTD 和CFAR 的特点、处理方式以及工程实现方法，同时对各种方法的优缺点进行了比较。其次根据雷达信号处理的特点，通过仿真进行 FPGA 和其它的芯片选型，在Altium Designer 6.9 软件下完成原理图和 PCB 的制作，并在 QuartusII 9.0 下完成FLASH 和 SDRAM 的软件接口设计。最后介绍了分布式算法，并以分布式算法为基础，详细阐述了脉冲压缩的编程以及在通用信号处理模块上实现的过程。关键词 通用信号处理模块；雷达信号处理；FPGA；脉冲压缩江苏科技大学工学硕士学位论文IIAbstractIIIAbstractIn recent years, the Programmable Logic Device developed rapidly, especially the FPGA, which not only realized miniaturization, low power consumption and high reliability of the signal processing machine, also as universal signal processing module flexible design, which based on FPGA, it is replacing ASIC on the market. FPGA is a kind of semi-custom integrated circuit, designers can completely control the design process, without any actual integrated circuit manufacturing equipment. Even though the radar signal processor with DSP processing core has been widely used, but its drawback is that real-time is not good, FPGA can solve this problem. Now FPGA develop rapidly, most existing FPGA integrated DSP module. The operability of FPGA as processing core used in universal signal processing module is strong.Based on radar signal processing demand, a universal signal processing module was designed and completed by author. The module uses a high-capacity FPGA as the core of signal processing, uses FLASH and SDRAM as external storage, uses SCM as bridge between FPGA and Computer. Through serial port, the designer can real-time debug and monitor.In order to complete this topic, the following aspects were studied in the dissertation.Firstly, analyze the characteristics of Radar signal processing detailed, we gain characteristics, processing method and project implementation of Pulse Compress, MTI/MTD and CFAR. Whats more, we have a view of the advantage and disadvantage between different methods.Secondly, according to the characteristics of Radar signal processing, we have finished FPGA and other chips selection through simulation. We have completed schematic and PCB production in the software of Altium Designer 6.9, and also completed software interface design between FPGA and FLASH , SDRAM in the software of QuartusII 9.0.In the end, we introduce DA algorithm, and elaborate on programming of the Pulse Compression as well as process implementation on Universal signal processing module based on DA algorithm.Key words Universal signal processing module; Radar signal processing; FPGA; Pulse Compression江苏科技大学工学硕士学位论文IV目录V目 录摘 要 .IAbstract .II第 1 章 绪 论 .11.1 雷达信号处理技术的发展概况 .11.2 雷达信号处理的发展趋势 .21.2.1 雷达信号处理机的发展趋势 .21.2.2 雷达信号处理功能进一步得到拓展 .21.2.3 可重构、可拓展的雷达信号处理模块将得到迅速发展 .31.3 可编程逻辑器件的简介 .31.3.1 PAL/GAL.31.3.2 CPLD/FPGA .41.3.3 可编程逻辑器件的设计流程 .41.3.4 FPGA 在雷达信号处理中的应用 .51.4 本文的主要工作 .6第 2 章 雷达信号处理特点介绍 .72.1 脉冲压缩的原理及特点 .72.1.1 脉冲压缩简介 .72.1.2 脉冲压缩原理 .72.1.3 脉冲压缩工程实现方法 .92.1.4 脉冲压缩的加权处理 .112.2 雷达杂波抑制原理及特点（MTI/MTD） .132.2.1 动目标显示（MTI） .132.2.2 动目标检测（MTD） .162.3 恒虚警（CFAR）原理及特点 .182.3.1 恒虚警介绍 .182.3.2 恒虚警检测原理 .192.3.3 恒虚警实现方法 .202.4 本章小结 .23第 3 章 通用信号处理模块的系统设计和芯片选型 .243.1 通用信号处理模块的系统设计 .24江苏科技大学工学硕士论文VI3.1.1 通用信号处理模块的设计思想来源 .243.1.2 以 FPGA 为核心的设计构想 .253.1.3 FPGA 芯片的选择 .263.1.4 通用信号处理模块框图介绍 .273.2 通用信号处理模块内部芯片选型 .293.2.1 存储器的选择 .293.2.2 A/D 和 D/A 的选择 .303.2.3 单片机的选择 .303.2.4 电源的选择 .313.2.5 模块其他芯片选择 .333.3 本章小结 .33第 4 章 通用信号处理模块的软硬件设计 .344.1 系统硬件设计 .344.1.1 FPGA 硬件设计 .344.1.2 存储电路设计 .374.1.3 A/D 和 D/A 转换电路设计 .394.1.4 单片机电路设计 .414.1.5 其它接口电路设计 .424.2 系统软件设计 .474.2.1 FLASH 的读写控制程序设计 .474.2.2 SDRAM 的读写控制程序设计 .514.3 通用信号处理模块 PCB 的制作 .574.3.1 PCB 板层的选择 .574.3.2 PCB 布局考虑 .584.3.3 PCB 布线考虑 .604.4 本章小结 .60第 5 章 通用信号处理模块功能实现实例 .615.1 分布式算法 .615.1.1 分布式算法原理 .615.1.2 分割查找表的分布式算法 .635.1.3 分布式算法分类 .645.2 基于 FPGA 的 FIR 滤波器的实现 .655.2.1 4 阶 FIR 滤波器的设计 .655.2.2 8 阶和高阶 FIR 滤波器的设计 .72目录VII5.3 64 阶脉冲压缩滤波器的设计实例 .735.3.1 匹配滤波器介绍 .735.3.2 64 阶数字脉冲压缩滤波器的实现方法 .745.4 本章小结 .78结束语 .79参考文献 .80致 谢 .82江苏科技大学工学硕士学位论文VIIICONTENTSIXContentsAbstract(Chinese) .IAbstract(English).IIChapter 1 Introduction.11.1 Development Overview of Radar signal processing.11.2 Development Trend of Radar singal processing .21.2.1 Radar signal processing machine development trend .21.2.2 Function of Radar processing will make further development .21.2.3 The reconfigurable，developing radar singal processing module will be further developed .31.3 Brief Introduction about Programmable Logic Device.31.3.1 PAL/GAL .31.3.2 CPLD/FPGA .41.3.3 Design flow about Programmable Logic Device .41.3.4 FPGA application in Radar signal processing .51.4 Main work of this Topic .6Chapter 2 Introduction about Characteristics of Radar Signal Processing.72.1 Basic Theory and Characteristics of Pulse Compression.72.1.1 Introduction about Pulse Compression .72.1.2 Bascic Theory of Pulse Compression .72.1.3 Project Implementation of Pulse Compression.92.1.4 The Weighted Pulse Compression .112.2 Basic Theory and Characteristics of the Radar Clutter Suppression(MTI/MTD).132.2.1 Moving Target Indication .132.2.2 Moving Target Detector.162.3 Basic Theory and Characteristics of Constant False Alarm Rate .182.3.1 Introduction of CFAR .182.3.2 Detection Principle of CFAR.192.3.3 Implementation Method of CFAR .202.4 Summary .23Chapter3 Universal Signal Processing Module System Design and Chip Selection .243.1 Universal Signal Processing Module System Design .243.1.1 Source of Design Ideas about Universal Signal Processing Module .243.1.2 Design Concept about FPGA as the Core.25江苏科技大学工学硕士学位论文X3.1.3 Chip Selection about FPGA.263.1.4 Block Diagram Description about Universal Signal Processing Module .273.2 Chip Selection about Universal Signal Processing Module.293.2.1 Memory Selection .293.2.2 A/D and D/A Selection .303.2.3 Single-chip Microcomputer Selection .303.2.4 Power Supply Selection .313.2.5 Other Chips Selection .333.3 Summary .33Chapter4 Software and Hardware Design about Universal Signal Processing Module.344.1 System Hardware Design.344.1.1 FPGAHardward Desgin .344.1.2 Memory Circuit Design .374.1.3 A/D and D/A Converter Circuit Design.394.1.4 Single-chip Microcomputer Circuit Design.414.1.5 Other Interface Circuit Design.424.2 System Software Design .474.2.1 Re