VGA显示器彩色信号发生器电路设计 专业英语论文.doc

vga显示器彩色信号发生器电路设计 【摘要】本设计完成了一个基于vhdl的vga显示控制模块，通过fpga控制图像信号与时序信号，软件的开发环境是altera公司的quartus 9.0。设计运用vhdl语言编程，配置加载fpga芯片，经fpga处理，信号通过电阻分压，由vga接口输出，设计的主控制器采用altera公司的cyclone ep3c10e144c8芯片。目的：通过对vga接口的显示控制设计，理解vga接口的时序工作原理，掌握通过计数器产生时序控制信号的方法。结果：通过完成整个设计，在最后验证阶段，通过两个开关的控制，可以在vga显示器上看到横彩条、竖彩条、方格（八种颜色）四种图像。关 键 词 vga； fpga； 时序控制； 电阻分压the vga display color signal generator circuit design abstract this design completed a vga display based on vhdl control module, through the fpga control of image signal and timing signal, software development environment is the altera company quartus 9.0. the design uses vhdl language programming, loaded configuration fpga chip, the fpga processing, signal through the resistance points pressure,through the vga interface output, the main controller design by altera company ep3c10e144c8 chip cyclone. objective: to vga display interface through control design, understanding of the succession of the working principle vga interface, master through the counter produces sequential control signal method. results: through the complete the whole design, in the last phase of verification, through the two switch control, can see on display in the vga striped, perpendicular striped, squares (eight kinds of color) four kind of image.key words vga; fpga; sequential control; resistance points pressure 41.1. system designa plan to ask: can the vga display shows eight color graphics (a type, square type), in this design through the expansion, adding the two control switch, used to realize the four models of striped display.system design scheme:(1) design ideas: the fpga displays of the vga interface to carry on the design, data flow only need in the whole system of internal flow, and dont need to rely on the computer, experiment system minimization, greatly reducing the size of the circuit board, and increase the reliability of system and design flexibility. vga is computer monitors common display standards, vga interface lcd monitor, crt monitor standard interface, through the vga control lcd, crt can make the whole system to become small and portable, make application range greatly expand. in the design of the serious, it is the need to put the real-time display images directly, in order to verify the correctness of the design, so as to meet the needs of all kinds of different application design.(2) each function blocks of division and composition: this design mainly by two module, the clock points frequency modules and display and control module.the clock module mostly used for 50 mhz clock binary system frequency signal sweep of the need to get vga 25 mhz frequency.1.2. vga display modulei vga interfacethe computer monitor shows many standard, the most common is vga. vga is video graphics array (video graphic array) abbreviations, vga industry standards for 640 hz * 480 hz * 60 hz mode, signal types for simulation type. the display card interface for 15 pin socket. interface as shown in figure:no. 1 vga interface diagram vga interface of 1, 2, 3 feet by d/a converter respectively output r, g, b three color digital signal, 13 feet by synchronizing signal line, 14 feet by a synchronized signal, 5, 6, 7, 8, 10 feet ground, the rest of the pins are hung up. vga display principlevga display, its lead wire with five of the elder brother of the signal: r, g, b (3 gezer signal), hs (line synchronized signal), vs (field synchronized signal). by r, g, b three gezer can combined from the color of any required.vga display in a line of image display to finish, with line synchronous signal line synchronization, go forward hand in hand line do vanishing, line for low level synchronous signal effectively. when scanning all falls, use synchronized signal field synchronization. and the scan back to the upper left of the screen, meanwhile, a vanishing, and preparing for the next scanning. a synchronous signal also for low level effective. line and a scan sequence diagram as shown in figure: no. 2 vga line, a scan sequence diagramindustry standard requirements of the vga frequency:the clock frequency (clock frequency) : 25.175 mhz (pixel output frequency)hangpin (line frequency) : 31469 hzchangpin (field frequency) : 59.94 (second image refresh frequency).2. unit circuit design(1) scanning boundary default: constant hsync_end : std_logic_vector(9 downto 0) := 0001011111; constant hdat_begin : std_logic_vector(9 downto 0) := 0010001111; constant hdat_end : std_logic_vector(9 downto 0) := 1100001111; constant hpixel_end : std_logic_vector(9 downto 0) := 1100011111; constant vsync_end : std_logic_vector(9 downto 0) := 0000000001; constant vdat_begin : std_logic_vector(9 downto 0) := 0000100010; constant vdat_end : std_logic_vector(9 downto 0) := 1000000010; constant vline_end : std_logic_vector(9 downto 0) := 1000001100;(2) the output generated 25 mhz pixels frequency (clock frequency of 50 mhz) :process begin wait until (clockevent and clock = 1); vga_clk = not vga_clk; end process(3) scanning:process begin wait until (vga_clkevent and vga_clk = 1); if (hcount_ov = 1) then hcount = 0000000000; else hcount = hcount + 0000000001; end if;end process; (4) the field scans: process begin wait until (vga_clkevent and vga_clk = 1); if (hcount_ov = 1) then if (vcount_ov = 1) then vcount = 0000000000; else vcount = vcount + 0000000001; end if; end if;end process; 3.software design dystem test(1) the design main use their learning development board, core for cyclone ep3c10e144c8.(2) the program flow charts are as follows:(3) vga module principle chart is as follows:(4) the pins are as follows:(5) simulation waveform figure as follows:(6) verification results are as follows:4. conclusions vga timing is to realize the design is the controller of the difficulty. because no data interface vga can signal, the display is through the scanning and field scans the mode of display to scan the control. so, the signal to the timing synchronization vga is strict, if synchronized signal not synchronous good, will display the data as a lost, even into chaos as that. therefore, we must use special vga controller to display the strict vga timing driver.second, to the design process must first have a whole design solutions. the first design engineering is divided into several small module, and then by his teammates to separate each module design, test and verify, summary. to work together to solve each module how to join together. in the test and s