基于vhdl语言的数字时钟设计说明书.doc

课程：CPLD与FPGA设计及应用实验：基于VHDL语言的数字时钟设计 学号：092030030姓名： 朱 峰 专业：信号与信息处理 学院：电子与信息学院2011年12月基于VHDL语言的数字时钟设计一：主要功能1：具有时、分、秒计数显示功能，以24小时循环计时。2：具有日期和星期显示功能。3：具有秒表功能4：具有调节日期，星期，小时，分钟，清零的功能。5：具有定时和闹铃的功能。二：结构框图控制单元使能信号数字时钟CLK时钟信号报警（闹铃）信号复位信号输出信号LED显示扬声器三：RTL图四：功能实现 4.1分频模块设计 本设计使用的输入时钟信号为50Mhz，经过分频产生两路时钟信号，其中一路为微秒计数时钟信号，一路为动态扫描时钟信号。同时模块有一输入控制信号，其功能是停止微秒计数时钟信号，以实现定时的功能。输入：clk_in 为50Mhz，setstop为微秒计数时能信号输出：clk_out1为1/60hz clk_out2为1khz源代码如下：library ieee;use ieee.std_logic_1164.all;entity div is port(clk_in,setstop: in std_logic; clk_out1,clk_out2: out std_logic);end entity div;architecture fun of div isconstant a:integer:=8333333;constant b:integer:=49999;signal c:integer range 0 to a;signal d:integer range 0 to b;beginprocess(clk_in,setstop) begin if(clk_in event and clk_in=1) then if( c+7500000)a and setstop=1) then c=c+1;clk_out1=1; else c=0;clk_out1=0; end if; end if;end process;process(clk_in) begin if(clk_in event and clk_in=1) then if d=b then d=d+1; clk_out2=1; else d=0;clk_out2=0; end if; end if;end process;end fun;4.2计时模块设计4.2.1 微秒计时模块 计数器的第一个模块为微秒计时模块，其实质为一个六十进制计数器。输入：clk为1/60hz，reset为清零复位键输出：ensecond为秒模块的进位信号 Daout为微妙输出显示信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity msecond isport(clk,reset:in std_logic; ensecond:out std_logic; daout:out std_logic_vector(6 downto 0);end entity msecond;architecture fun of msecond is signal count:std_logic_vector(6 downto 0); signal enmin_1:std_logic;beginprocess(clk,reset)begin if(reset=0)then count=0000000; elsif(clk event and clk=1)then if(count(3 downto 0)=1001)then if(count16#60#)then if(count=1011001)then enmin_1=1;count=0000000; else count=count+7; end if; else count=0000000; end if; elsif(count16#60#)then count=count+1 ; enmin_1=0 ; else count=0000000; end if; end if;end process; daout=count; ensecond=enmin_1 ;end fun;4.2.2 秒计时模块 计数器的第二个模块为秒计时模块，其实质为一个六十进制计数器。输入：clk为秒进位信号，reset为清零复位键，setmin为调分信号，setclk为消抖时钟输出：enmin为分模块的进位信号 daout为秒输出显示信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport(clk,setclk,reset,setmin:in std_logic; enmin:out std_logic; daout:out std_logic_vector(6 downto 0);end entity second;architecture fun of second is signal count:std_logic_vector(6 downto 0); signal enmin_1,enmin_2:std_logic;beginprocess(clk,reset,setmin)begin if(reset=0)then count=0000000; elsif(clk event and clk=1)then if(count(3 downto 0)=1001)then if(count16#60#)then if(count=1011001)then enmin_1=1;count=0000000; else count=count+7; end if; else count=0000000; end if; elsif(count16#60#)then count=count+1 ; enmin_1=0 ; else count=0000000; end if; end if;end process;process(setclk,setmin)begin if(setclk event and setclk=1) then enmin_2=not setmin ; end if; end process; daout=count; enmin=(enmin_1 or enmin_2);end fun;4.2.3 分计时模块 计数器的第三个模块为秒计时模块，其实质为一个六十进制计数器。输入：clk为分进位信号，reset为清零复位键，sethour为调时信号，setclk为消抖时钟输出：enhour为小时模块的进位信号 daout为分输出显示信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute isport( clk,setclk,reset,sethour:in std_logic; enhour:out std_logic; daout:out std_logic_vector(6 downto 0);end entity minute;architecture fun of minute is signal count:std_logic_vector(6 downto 0); signal enhour_1,enhour_2:std_logic;beginprocess(clk,reset)begin if(reset=0)then count=0000000; elsif(clk event and clk=1)then if(count(3 downto 0)=1001)then if(count16#60#)then if(count=1011001)then enhour_1=1; count=0000000; else count=count+7; end if; else count=0000000; end if; elsif(count16#60#)then count=count+1; enhour_1=0 ; else count=0000000; end if; end if; end process;process(setclk,sethour)begin if(setclk event and setclk=1) then enhour_2=not sethour ; end if; end process; daout=count; enhour=(enhour_1 or enhour_2);end fun;4.2.4小时计时模块 计数器的第四个模块为小时计时模块，其实质为一个二十四进制计数器。输入：clk为分进位信号，reset为清零复位键，setweek为调小时信号，setclk为消抖时钟输出：enweek为日期模块的进位信号 daout为小时输出显示信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour isport( clk,setclk,reset,setweek:in std_logic; enweek:out std_logic; daout:out std_logic_vector(6 downto 0);end entity hour;architecture fun of hour is signal count:std_logic_vector(6 downto 0); signal enweek_1,enweek_2:std_logic;begin process(clk,reset)begin if(reset=0)then count=0000000; elsif(clk event and clk=1)then if(count(3 downto 0)=1001) and (count16#23# )then count=count+7; elsif (count=0100011)then enweek_1=1;count=0000000; elsif(count16#23#)then count=count+1; enweek_1=0; else count=0000000; end if; end if;end process;process(setclk,setweek)begin if(setclk event and setclk=1) then enweek_2=not setweek; end if; end process; daout=count; enweek=(enweek_1 or enweek_2) ;end fun;4.3日期和星期模块设计 4.3.1 星期显示模块 星期显示模块其实质为一个七进制计数器。输入：clk为日期进位信号，reset为清零复位键输出：weeoutk为星期输出显示信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity weeker is port(clk:in std_logic; reset:in std_logic; weekout:out std_logic_vector(3 downto 0);end entity weeker;architecture fun of weeker issignal count:std_logic_vector(3 downto 0);beginprocess(clk,reset) begin if(reset=0)then count=0001; elsif(clk event and clk=1)then if (count16#7#) then count=count+1; else count=0001; end if; end if; end process; weekout=count; end fun;4.3.2 日期显示模块 日期显示模块其实质为一个十二选一选择器。输入：clk为日期进位信号，reset为清零复位键输出：monthout 为月输出显示信号 Dateout为日输出显示信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity date is port(clk:in std_logic; reset:in std_logic; monthout:out std_logic_vector(4 downto 0); dateout:out std_logic_vector(5 downto 0);end entity date;architecture fun of date issignal dount:std_logic_vector(4 downto 0);signal count:std_logic_vector(5 downto 0);beginprocess(clk,reset) begin if(reset=0)then count=000001;dount=00001; elsif(clk event and clk=1 and dount=00001 )then if(count(3 downto 0)=1001) and (count16#31# )then count=count+7; elsif (count16#31#) then count=count+1; else count=000001;dount=dount+1;end if; elsif(clk event and clk=1 and dount=00010 )then if(count(3 downto 0)=1001) and (count16#29# )then count=count+7; elsif (count16#29#) then count=count+1; else count=000001;dount=dount+1;end if; elsif(clk event and clk=1 and dount=00011 )then if(count(3 downto 0)=1001) and (count16#31# )then count=count+7; elsif (count16#31#) then count=count+1; else count=000001;dount=dount+1;end if; elsif(clk event and clk=1 and dount=00100 )thenif(count(3 downto 0)=1001) and (count16#30# )then count=count+7; elsif (count16#30#) then count=count+1; else count=000001;dount=dount+1; end if; elsif(clk event and clk=1 and dount=00101 )then if(count(3 downto 0)=1001) and (count16#31# )then count=count+7; elsif (count16#31#) then count=count+1; else count=000001;dount=dount+1; end if; elsif(clk event and clk=1 and dount=00110 )then if(count(3 downto 0)=1001) and (count16#30# )then count=count+7; elsif (count16#30#) then count=count+1; else count=000001;dount=dount+1;end if; elsif(clk event and clk=1 and dount=00111 )then if(count(3 downto 0)=1001) and (count16#31# )then count=count+7; elsif (count16#31#) then count=count+1; else count=000001;dount=dount+1;end if; elsif(clk event and clk=1 and dount=01000 )then if(count(3 downto 0)=1001) and (count16#31# )then count=count+7; elsif (count16#31#) then count=count+1; else count=000001;dount=dount+1;end if; elsif(clk event and clk=1 and dount=01001 )then if(count(3 downto 0)=1001) and (count16#30# )then count=count+7; elsif (count16#30#) then count=count+1; else count=000001;dount=dount+1; end if; elsif(clk event and clk=1 and dount=01010 )then if(count(3 downto 0)=1001) and (count16#31# )then count=count+7; elsif (count16#31#) then count=count+1; else count=000001;dount=dount+1;end if; elsif(clk event and clk=1 and dount=01011 )then if(count(3 downto 0)=1001) and (count16#30# )then count=count+7; elsif (count16#30#) then count=count+1; else count=000001;dount=dount+1; end if; elsif(clk event and clk=1 and dount=01100 )then if(count(3 downto 0)=1001) and (count16#31# )then count=count+7; elsif (count16#31#) then count=count+1; else count=000001;dount=dount+1;end if;end if; end process; monthout=dount; dateout=count; end fun;4.4扫描显示模块设计 该模块的作用是将时钟产生的微秒、秒、分、小时、星期和日期信号以扫描的形式显示输出。其中一控制信号实现数码管的复用，控制显示微秒、秒、分、小时或星期、日期。输入：clk1为扫描时钟，reset为清零复位键，ms、sec、min、hour、month、date、week分别为微秒、秒、分、小时、月、日、星期显示信号，showweek为控制信号输出：dp为数码管小数点显示信号 led为七段数码管显示信号 sel为位选信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity seltime isport( clk1,reset,showweek:in std_logic; ms,sec,min,hour:in std_logic_vector(6 downto 0); month:in std_logic_vector(4 downto 0); date:in std_logic_vector(5 downto 0); week:in std_logic_vector(3 downto 0); dp:out std_logic; led:out std_logic_vector(6 downto 0); sel:out std_logic_vector(7 downto 0);end entity seltime ;architecture fun of seltime issignal count:std_logic_vector(3 downto 0);signal daout:std_logic_vector(3 downto 0);signal d:std_logic_vector(4 downto 0);beginp1 : process(clk1,reset)begin if(reset=0)then count1101)then count=0000; d=count&showweek ; else count=count+1; ddaout=ms(3 downto 0);sel=01111111;dpdaout(3)=0;daout(2 downto 0)=ms(6downto4);sel=10111111;dpdaout=sec(3 downto 0);sel=11111110;dpdaout(3)=0;daout(2downto0)=sec(6 downto 4);sel=11111101;dpdaout=min(3 downto 0);sel=11111011;dpdaout(3)=0;daout(2downto0)=min(6downto 4);sel=11110111;dpdaout=hour(3 downto 0);sel=11101111;dpdaout(3downto2)=00;daout(1downto0)=hour(5downto4);sel=11011111;dpdaout=week;sel=01111111;dpdaout=date(3 downto 0);sel=11111110;dpdaout(3downto2)=00;daout(1downto0)=date(5downto4);sel=11111101;dpdaout=month(3 downto 0);sel=11111011;dpdaout(3 downto 1)=000;daout(0)=month(4);sel=11110111;dpselledledledledledledledledledlednull;end case;end process p3;end fun;4.5 整点报时模块设计 该模块的作用是当时钟计数到整点时蜂鸣器报警，以实现整点报时功能。输入：clk计数时钟信号，speaksec秒输出信号，speakmin分输出信号输出：报警信号源代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speaker is port(clk:in std_logic; speaksec:in std_logic_vector(6 downto 0); speakmin:in std_logic_vector(6 downto 0); speak:out std_logic);end entity speaker;architecture fun of speaker isbeginprocess(clk,speakmin)begin if(clk event and clk=1)then if(speakmin=0000000 and speaksec=0000000)then speak=1;else speakclk_in, setstop=setstop, clk_out1=clk00, clk_out2=clk01); u2:msecond port map (clk=clk00, reset=reset, ensecond=ensecond_re, daout=da0out);u3:second port map (clk=ensecond_re, setclk=clk01, reset=reset, setmin=setmin, enmin=enmin_re, daout=dalout);u4:minute port map (clk=enmin_re, setclk=clk01, reset=reset, sethour=sethour, enhour=enhour_re, daout=dallout);u5:hour port map (clk=enhour_re, setclk=clk01, reset=reset, setweek=setweek, enweek=enweek_re, daout=dalllout);u6:weeker port map (clk=enweek_re, reset=reset, weekout=dallllout);u7:date port map (clk=enweek_re, reset=reset, monthout=month0out, dateout=date0out);u8:seltime port map(clk1=clk01, reset=reset, showweek=showweek, ms=da0out, sec=dalout, min=dallout, hour=dalllout, week=dallllout, date=date0out, month=month0out, sel=sel, led=led, dp=dp);u9:speaker port map(clk=clk01, speaksec=dalout, speakmin=dallout, speak=speak);end a; 39大学本科生毕业设计（论文）撰写规范本科生毕业设计（论文）是学生在毕业前提交的一份具有一定研究价值和实用价值的学术资料。它既是本科学生开始从事工程设计、科学实验和科学研究的初步尝试，也是学生在教师的指导下，对所进行研究的适当表述，还是学生毕业及学位资格认定的重要依据。毕业论文撰写是本科生培养过程中的基本训练环节之一，应符合国家及各专业部门制定的有关标准，符合汉语语法规范。指导教师应加强指导，严格把关。1、论文结构及要求论文包括题目、中文摘要、外文摘要、目录、正文、参考文献、致谢和附录等