EDA课程设计--秒表设计.doc

EDA课程设计报告 题目：秒表设计 班级：通信11-3小组成员：易新会、王伟、陈虹余、迪拉热 指导老师：黄志华 学院：信息科学与工程学院2014年1月1日内容一：设计任务与要求 秒表的逻辑结构比较简单，它主要由、显示译码器、分频器、十进制计数器、报警器和六进制计数器组成。在整个秒表中最关键是如何获得一个精确的100Hz计时脉冲，除此之外，整个秒表还需要一个启动信号和一个归零信号，以便能够随时启动及停止。秒表有六个输出显示，分别为百分之一秒，十分之一秒、秒、十秒、分、十分，所以共有6个计数器与之对应，6个个计数器全为BCD码输出，这样便于同时显示译码器的连接。当计时达60分钟后，蜂鸣器鸣响3声。二：设计原理 本系统采用自上向下的设计方案，系统的整体设计组装原理图如图2-1所示，它主要由控制模块，时基分屏模块，计时模块和显示模块四部分组成。各模块分别完成控制，分屏，计时和显示的功能 设计原理图 3、 程序模块1、控制模块程序library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity ctrl is port(clr,clk,sp:in std_logic; en:out std_logic);end ctrl;architecture behave of ctrl is type states is (s0,s1,s2,s3); signal current_state,next_state:states; begin com:process(sp,current_state) begin case current_state iswhen s0=en=0;if sp=1 then next_state=s1;else next_stateen=1;if sp=1 then next_state=s1;else next_stateen=1;if sp=1 then next_state=s3;else next_stateen=0;if sp=1 then next_state=s3;else next_state=s0;end if; end case; end process;synch:process(clk) begin if clr=1 then current_state=s0; elsif clkevent and clk=1 thencurrent_state=next_state; end if;end process;end behave;2、时基分频模块程序library ieee;use ieee.std_logic_1164.all;entity cb10 isport(clk: in std_logic; co: buffer std_logic);end cb10;architecture art of cb10 issignal counter:integer range 0 to 49999;begin process(clk) begin if (clk=1 and clkevent) then if counter=49999 thencounter=0;co= not co; elsecounter=counter+1; end if; end if; end process;end art;3、计时模块的程序1）、十进制计数器library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cdu10 isport(clk,clr,en: in std_logic;cn: out std_logic;count10: out std_logic_vector(3 downto 0);end cdu10;architecture art of cdu10 issignal temp:std_logic_vector(3 downto 0);beginprocess(clk,clr)beginif clr=1 then temp=0000;cn=1001 then temp=0000;cn=1; else temp=temp+1; cn=0; end if; end if; end if; count10=temp;end process;end art;2）、六进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cdu6 isport(clk,clr,en: in std_logic;cn: out std_logic; count6: out std_logic_vector(3 downto 0);end cdu6;architecture art of cdu6 issignal temp:std_logic_vector(3 downto 0);begin process(clk,clr)beginif clr=1 then temp=0000;cn=0; elsif (clkevent and clk=1) thenif en=1 then if temp=0110 then temp=0000;cn=1; else temp=temp+1;cn=0; end if; end if; end if; count6=temp; end process; end art;3）计时器程序library ieee;use ieee.std_logic_1164.all;entity count is port(clk:in std_logic; clr:in std_logic;en:in std_logic;S_10ms:out std_logic_vector(3 downto 0);S_100ms:out std_logic_vector(3 downto 0);S_1s:out std_logic_vector(3 downto 0);S_10s:out std_logic_vector(3 downto 0);M_1min:out std_logic_vector(3 downto 0);M_10min:out std_logic_vector(3 downto 0);end count;architecture art of count is component cdu10 port(clk,clr,en: in std_logic;cn: out std_logic;count10: out std_logic_vector(3 downto 0); end component cdu10; component cdu6 port(clk,clr,en: in std_logic;cn: out std_logic; count6: out std_logic_vector(3 downto 0); end component cdu6;signal A,B,C,D,E,F:std_logic;begin U1:cdu10 port map (clk,clr,en,A,S_10ms);U2:cdu10 port map (A,clr,en,B,S_100ms);U3:cdu10 port map (B,clr,en,C,S_1s);U4:cdu6 port map (C,clr,en,D,S_10s);U5:cdu10 port map (D,clr,en,E,M_1min);U6:cdu10 port map (E,clr,en,F,M_10min);end art;4、显示模块程序1)七段译码驱动器程序library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned; entity bcd7 is port(bcd:in std_logic_vector(3 downto 0); led:out std_logic_vector(6 downto 0); end bcd7 ; architecture art of bcd7 is begin led= 0111111 when bcd=0000else 0000110 when bcd=0001else 1011011 when bcd=0010else 1001111 when bcd=0011else 1100110 when bcd=0100else 1101101 when bcd=0101else 1111101 when bcd=0110else0000111 when bcd=0111else1111111 when bcd=1000else1101111 when bcd=1001else0000000;end art; 2）数据选择器程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_UNSIGNED.all;entity mulx is port(clk:in std_logic; clr:in std_logic;en:in std_logic;S_10ms:in std_logic_vector(3 downto 0);S_100ms:in std_logic_vector(3 downto 0);S_1s:in std_logic_vector(3 downto 0);S_10s:in std_logic_vector(3 downto 0);M_1min:in std_logic_vector(3 downto 0);M_10min:in std_logic_vector(3 downto 0);outbcd:out std_logic_vector(3 downto 0);seg:out std_logic_vector(2 downto 0);end mulx;architecture art of mulx issignal count:std_logic_vector(2 downto 0);beginprocess(clk)beginif (clr=1) then count=111;elsif (clk=1and clkevent) thenif en=1 thenif count=101 thencount=000; else countoutbcd=S_10ms; segoutbcd=S_100ms; segoutbcd=S_1s; segoutbcd=S_10s; segoutbcd=M_1min; segoutbcd=M_10min; segnull;end case;end if;end process;end art;5、 顶层设计源程序library ieee;use ieee.std_logic_1164.all;entity stopwatch is port (sp:in std_logic ; clr:in std_logic; clk:in std_logic; led:out std_logic_vector(6 downto 0); seg:out std_logic_vector(2 downto 0);end stopwatch;architecture art of stopwatch is component ctrl port(clr:in std_logic ; clk:in std_logic ;sp:in std_logic ;en:out std_logic ); end component; component cb10 port(clk:in std_logic; co:out std_logic); end component; component count port (clk:in std_logic; clr:in std_logic; en:in std_logic; S_10ms:out std_logic_vector(3 downto 0); S_100ms:out std_logic_vector(3 downto 0); S_1s:out std_logic_vector(3 downto 0); S_10s:out std_logic_vector(3 downto 0); M_1min:out std_logic_vector(3 downto 0); M_10min:out std_logic_vector(3 downto 0); end component; component bcd7 port(bcd:in std_logic_vector(3 downto 0); led:out std_logic_vector(6 downto 0); end component; component mulx port (clr:in std_logic; clk:in std_logic; en:in std_logic; S_10ms:in std_logic_vector(3 downto 0);S_100ms:in std_logic_vector(3 downto 0);S_1s:in std_logic_vector(3 downto 0);S_10s:in std_logic_vector(3 downto 0);M_1min:in std_logic_vector(3 downto 0);M_10min:in std_logic_vector(3 downto 0); outbcd:out std_logic_vector(3 downto 0); seg:out std_logic_vector(2 downto 0); end component;signal c,e:std_logic;signal ms10_s,ms100_s:std_logic_vector(3 downto 0);signal s1_s,s10_s:std_logic_vector(3 downto 0);signal min1_s,min10_s:std_logic_vector(3 downto 0);signal bcd_s,s:std_logic_vector(3 downto 0);beginu0:ctrl port map(clr,clk,sp,e);u1:cb10 port map(clk,c);u2:count port map(c,clr,e,ms10_s,ms100_s,s1_s,s10_s,min1_s,min10_s);u3:mulx port map(clr,clk,e,ms10_s,ms100_s,s1_s,s10_s,min1_s,min10_s,bcd_s,seg);u4:bcd7 port map (bcd_s,led);end art;4、 设计解决的关键问题本次设计的关键性问题是分频和顶层文件的设计，在分频代码段中可以看出我们本次采用的主频率是5MHZ。1/100秒的频率为100HZ所以只需要用5MHZ乘以1/50000即可得到100HZ的分频信号，即1/100秒。数码管显示部分的关键就是弄清楚每个数字对应的二进制代码，刚开始我们用画原理图的方法进行顶层文件设计，完成了实验，而后又尝试用VHDL语言进行程序设计，