外文翻译---具有8KB 系统可编程 Flash 的8位微控制器.docx

附录A ATmega8The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle.The resulting architecture is more code efficient while achieving throughputs up toten times faster than conventional CISC microcontrollers.The ATmega8 provides the following features:8K bytes of In-System Programmable Flash with Read-While-Write capabilities,512 bytes of EEPROM,1K byte of SRAM,23general purpose I/O lines,32 general purpose working registers, three flexibleTimer/Counters with compare modes, internal and external interrupts, a serial programmableUSART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eightchannels in TQFP and MLF packages) where four (six) channels have 10-bit accuracyand two channels have 8-bit accuracy, a programmable Watchdog Timer with InternalOscillator, an SPI serial port, and five software selectable power saving modes. The Idlemode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interruptsystem to continue functioning. The Power-down mode saves the register contents butfreezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer andADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.The device is manufactured using Atmels high density non-volatile memory technology.The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security.When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts.All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction RETI is executed.There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority.The second type of interrupts will trigger as long as the interrupt condition is present.These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.Note that the Status Register is not automatically stored when entering an interrupt routine,nor restored when returning from an interrupt routine. This must be handled by software.When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I-bit in SREG is set.The ATmega8 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16- or 32-bits wide, the Flash is organized as 4K x 16 bits. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory,and the next 1024 locations address the internal data SRAM.The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.The direct addressing reaches the entire data space.The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.When using register indirect addressing modes with automatic pre-decrement and postincrement,the address registers X,Y and Z are decremented or incremented.The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega8 are all accessible through all these addressing modes.The ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described bellow, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.“Memory Programming” on page 219 contains a detailed description on EEPROM Programmingin SPI- or Parallel Programming mode.All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 -0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers,the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchronously when clkI/O is halted, enabling TWI address reception in all sleep modes.XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 11. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a full rail-to-rail swing on the output. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces power consumption considerably. This mode has a limited frequency range and it cannot be used to drive other clock buffers.For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.附录B具有8KB 系统可编程 Flash 的8位微控制器AVR 内核具有丰富的指令集和32 个通用工作寄存器。所有的寄存器都直接与算逻单元(ALU) 相连接，使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。这种结构大大提高了代码效率，并且具有比普通的CISC 微控制器最高至10 倍的数据吞吐率。ATmega8 有如下特点：8K 字节的系统内可编程Flash( 具有同时读写的能力，即RWW)，512 字节 EEPROM，1K 字节 SRAM，32 个通用I/O 口线，32 个通用工作寄存器，三个具有比较模式的灵活的定时器/ 计数器(T/C), 片内/ 外中断，可编程串行USART，面向字节的两线串行接口， 10 位6 路 (8 路为TQFP 与MLF 封装)ADC，具有片内振荡器可编程看门狗定时器，一个SPI 串端口，以及五种可以通过软件进行选择的省电模式。工作于空闲模式时CPU 停止工作，而SRAM、T/C、 SPI 端口以及中断系统继续工作；掉电模式时晶体振荡器停止振荡，所有功能除了中断和硬件复位之外都停止工作；在省电模式下，异步定时器继续运行，允许用户保持一个时间基准，而其余功能模块处于休眠状态； ADC 噪声抑制模式时终止CPU 和除了异步定时器与ADC 以外所有I/O 模块的工作，以降低ADC 转换时的开关噪声； Standby 模式下只有晶体或谐振振荡器运行，其余功能模块处于休眠状态，使得器件只消耗极少的电流，同时具有快速启动能力。本芯片是以Atmel 高密度非易失性存储器技术生产的。片内ISP Flash 允许程序存储器通过ISP 串行接口，或者通用编程器进行编程，也可以通过运行于AVR 内核之中的引导程序进行编程。引导程序可以使用任意接口将应用程序下载到应用Flash存储区(Application Flash Memory)。在更新应用Flash存储区时引导Flash区(Boot Flash Memory)的程序继续运行，实现了RWW 操作。 通过将8 位RISC CPU 与系统内可编程的Flash 集成在一个芯片内，ATmega8 成为一个功能强大的单片机，为许多嵌入式控制应用提供了灵活而低成本的解决方案。ATmega8 具有一整套的编程与系统开发工具，包括：C 语言编译器、宏汇编、 程序调试器/ 软件仿真器、仿真器及评估板。AVR有不同的中断源。每个中断和复位在程序空间都有独立的中断向量。所有的中断事件都有自己的使能位。当使能位置位，且状态寄存器的全局中断使能位I 也置位时，中断可以发生。根据程序计数器PC 的不同，在引导锁定位BLB02 或BLB12 被编程的情况下，中断可能被自动禁止。这个特性提高了软件的安全性。任一中断发生时全局中断使能位I 被清零，从而禁止了所有其他的中断。用户软件可以在中断程序里置位I 来实现中断嵌套。此时所有的中断都可以中断当前的中断服务程序。执行RETI 指令后I 自动置位。从根本上说有两种类型的中断。第一种由事件触发并置位中断标志。对于这些中断，程序计数器跳转到实际的中断向量以执行中断处理程序，同时硬件将清除相应的中断标志。中断标志也可以通过对其写的方式来清除。当中断发生后，如果相应的中断使能位为“0”，则中断标志位置位，并一直保持到中断执行，或者被软件清除。类似的，如果全局中断标志被清零，则所有已发生的中断都不会被执行，直到I 置位。然后挂起的各个中断按中断优先级依次执行。第二种类型的中断则是只要中断条件满足，就会一直触发。这些中断不需要中断标志。若中断条件在中断使能之前就消失了，中断不会被触发。AVR 退出中断后总是回到主程序并至少执行一条指令才可以去执行其他被挂起的中断。要注意的是，进入中断服务程序时状态寄存器不会自动保存，中断返回时也不会自动恢复。这些工作必须由用户通过软件来完成。使用CLI 指令来禁止中断时，中断禁止立即生效。没有中断可以在执行CLI 指令后发生，即使它是在执行CLI 指令的同时发生的。下面的例子说明了如何在写EEPROM 时使用这个指令来防止中断发生以避免对EEPROM 内容的破坏。AVR 中断响应时间最少为4 个时钟周期。4 个时钟周期后，程序跳转到实际的中断处理例程。在这4 个时钟期期间PC 自动入栈。在通常情况下，中断向量为一个跳转指令，此跳转需要3 个时钟周期。如果中断在一个多时钟周期指令执行期间发生，则在此多周期指令执行完毕后MCU 才会执行中断程序。若中断发生时MCU 处于休眠模式，中断响应时间还需增加4 个时钟周期。此外还要考虑到不同的休眠模式所需要的启动时间。中断返回需要4 个时钟。在此期间PC( 两个字节) 将被弹出栈，堆栈指针加二，状态寄存器S