微机原理ch06MEMORYANDMEMORYINTERFACING.docVIP

6 MEMORY AND MEMORY INTERFACING6.1 SEMICONDUCTOR MEMORY FUNDAMENTALSIn the design of all computers, semiconductor memories are used as primary storage for code and data. Semiconductor memories are connected directly to the CPU and they are the memory that the CPU first asks for information (code and data). For this reason, semiconductor memories are referred to as primary memory.6.1.1 Memory capacityThe number of bits that a semiconductor memory chip can store is called its chip capacity. It can be in units of Kbits (kilobits), Mbits (megabits), and so on.This must be distinguished from the storage capacity of computers. While the memory capacity of a memory IC chip is always given in bits, the memory capacity of a computer is given in bytes.6.1.2 Memory organizationMemory chips are organized into a number of locations within the IC. Each location can hold 1 bit, 4 bits, 8 bits, or even 16 bits, depending on how it is designed internally.The number of bits that each location within the memory chip can hold is always equal to the number of data pins on the chip.How many locations exists inside a memory chip depends on the number of address pins. The number of locations within a memory IC always equals 2x where x is the number of address pins.Therefore, the total number of bits that a memory chip can store is equal to the number of locations times the number of data bit per location.To summary:1) Each memory chip contains 2x locations, where x is the number of address pins on the chip.2) Each location contains y bits, where y is the number of data pins on the chip.3) The entire chip will contain 2x y bits, where x is the number of address pins on the chip and y is the number of data pins on the chip.4) The 2x y is referred to as the organization of the memory chip, where x is the number of address pins on the chip and y is the number of data pins on the chip.5) For 2x , use 表 61 to give the number of locations in K or M units.表 61 Powers of 2x2x101K112K124K138K1416K1532K1664K17128K18256K19512K201M212M224M238M2416M324GExample 1A given memory chip has 12 address pins and 8 data pins. Find:1) the organization2) the capacitySolution:1) This memory chip has 4096 locations (212 = 4096), and each location can hold 8 bits of data. This organization of 4096 8, often represented as 4K8.2) The capacity is equal to 32K bits since there is a total of 4K locations and each locations can hold 8 bits of data.Example 2A 512K memory chip has 8 pins for data. Find:1) the organization2) the number of address pins for this memory chipSolution:1) A memory chip with 8 data pins means that each location within the chip can hold 8 bits of data. To find the number of locations within this memory chip, divide the capacity by the number of data pins. 512K/8 = 64K; therefore, the organization for this memory chip is 64K8.2) This chip has 16 address lines since 216 = 64K.6.1.3 SpeedOne of the most important characteristics of a memory chip is the speed at which data can be accessed from it.To access the data, the address is presented to the address pins, and after a certain amount of time has elapsed, the data show up at the data pins. The shorter this elapsed time, the better, and consequently, the more expensive the memory chip.The speed of the memory chip is commonly referred to as its access time. The access time of memory chips varies from a few nanoseconds to hundreds of nanoseconds, depending on the IC technology used in the design and fabrication.6.1.4 ROM (read-only memory)ROM is a type of memory that does not lose its contents when the power is turned off. For this reason, ROM is also called nonvolatile memory.There are different types of read-only memory, such as PROM, EPROM, EEPROM, flash ROM, and mask ROM.6.1.5 PROM (programmable ROM) or OTP ROMPROM is referred to the kind of ROM that the user can burn information into, PROM is a user-programmable memory.For every bit of the PROM, there exists a fuse. PROM is programmed by blowing the fuses (blow a fuse 使保险丝熔断). If the information burned into PROM is wrong, PROM must be discarded since internal fuses are blown permanently. For this reason, PROM is also referred to as OTP (one-time programmable). The process of programming ROM is also called burning ROM and requires special equipment called a ROM burner or ROM programmer.6.1.6 EPROM (erasable programmable ROM)EPROM was invented to allow changes in the contents of PROM after it is burned. In EPROM, one can program the memory chip and erase it thousands of times.All EPROM chip have a window that is used to shine ultraviolet (UV)(紫外线) radiation to erase its contents. The only problem with EPROM is that erasing its contents can take up to 20 minutes. EPROM is also referred to as UV-erasable EPROM or simply UV-EPROM.The major disadvantage of UV-EPROM is that it cannot be programmed while in the system board (motherboard).6.1.7 EEPROM (electrically erasable programmable ROM)EEPROM has several advantages over EPROM, such as the fact that its method of erasure is electrical and therefore instant.6.1.8 Flash memorySince the early 1990s, flash ROM has become a popular user-programmable memory chip. The process of erasure of the entire contents takes only a few seconds, or one might say in a flash, hence its name: Flash memory.The erasure method is electrical and for this reason it is sometimes referred to as Flash EEPROM. To avoid confusion, it is commonly called Flash ROM.The major difference between EEPROM and Flash memory is the fact that when flash memorys contents are erased the entire device is erased, in contrast to EEPROM, where one can erase a desired section or byte. Although there are some flash memories recently made available in which the contents are divided into blocks and the erasure can be done by block, unlike EEPROM, no byte erasure option is available.Some designers believe that flash memory will replace the hard disk as mass storage medium. This would increase the performance of computers tremendously, since flash memory is semiconductor memory with access range of tens of milliseconds. For this to happen, flash memorys program/erase cycles must become infinite, just like hard disks. Program/erase cycle refers to the number of times that a chip can be erased and programmed before it becomes unusable.At this time, the program/erase cycle is 500,000 for flash and EEPROM, 2000 for UV-EPROM, and infinite for RAM and disks.表 62 Examples of ROM memory chipsTypePart NumberSpeed (ns)CapacityOrganizationPinsVppUV-EPROM271645016K2K824252716-135016K2K824252716B45016K2K82412.52732A-4545032K4K824212732A-2020032K4K8242127C3245032K4K824252764A-2525064K8K82812.527C64-1515064K8K82812.527128-20200128K16K82812.527C128-25250128K16K82812.527256-20200256K32K82812.527C256-20200256K32K82812.527512-25250512K64K82812.527C512-25250512K64K82812.527C010-121201M128K83212.527C201-121202M256K83212.527C410-121204M512K83212.5EEPROM28C16A-2525016K2K82452864A25064K8K828528C256-15150256K32K828528C256-25250256K32K8285Flash ROM28F256-20200256K32K8321228F256-15150256K32K8321228F010-202001M128K8321228F020-151502M256K83212In part numbers, C referred to CMOS technology, where 27xx is for UV-EPROM, 28xx for EEPROM.图 61 6116 2K x 8 SRAM6.1.9 Mask ROMMask ROM referred to a kind of ROM whose contents are programmed by the IC manufacturer. In other word, it is not user-programmable ROM. The terminology mask is used in IC fabrication.6.1.10 RAM (random access memory)RAM memory is called volatile memory since cutting off power to the IC will mean the loss of data.There three types of RAM:l static RAM (SRAM)l dynamic RAM (DRAM)l NV-RAM (nonvolatile RAM)6.1.11 SRAM (static RAM)Storage cells in static RAM memory are made of flip-flops and therefore do not require refreshing in order to keep their data. The problem with the use of flip-flops for storage cells is that each cell requires at least 6 transistors to build, and the cell holds only 1 bit of data. In recent years, the cells have been made of 4 transistors, which is still too many.The use of 4-transistor cell plus the use CMOS technology has given birth to a high-capacity SRAM, but the capacity of SRAM is far below DRAM. SRAMs are widely used for cache memory.图 62 6116 2K x 8 SRAMA0-A10 are for address inputs, where 11 address lines gives 2K.I/O0-I/O7 are for data I/O, while 8-bit data lines gives an organization of 2K x 8.WE (write enable) is for writing data into SRAM (active-low).OE (output enable) is for reading data out of SRAM (active-low)CS (chip select) is used to select the memory chip.The following are steps to write data into SRAM:1) Provide the addresses to pins A0-A10.2) Activate the CS pin.3) Make WE = 0 while OE = 14) Provide the data to pins I/O0-I/O7.5) Make WE = 1 and data will be written into SRAM on the positive edge of the WE signal.图 63 Memory write timing for SRAMThe following are steps to read data from SRAM:1) Provide the addresses to pins A0-A10. This is the start of the access time (tAA)2) Activate the CS pin.3) While WE = 1, a high-to-low pulse on the OE pin will read the data out of the chip.图 64 Memory read timing for SRAMIn the 6116 SRAM, the access time, tAA, is measured as the time elapsed from the mount the address is provided to the address pins to the moment that the data is available at the data pins. The speed for the 6116 chip can vary from 100ns to 15ns.The read cycle time (tRC) is defined as minimum amount of time required to read one byte of data. That is, from the moment we apply the addresses of the byte to the moment we can begin the next operation.In SRAM for which tAA = 100ns, tRC is also 100ns. This implies that we can read the contents of consecutive address locations with each taking no more than 100ns. Hence, in SRAM and ROM, tAA = tRC . They are not equal in DRAM.6.1.12 DRAM (dynamic RAM)Since the early days of the computer, the need for huge, inexpensive read/write memory was a major preoccupation (当务之急) of computer designers. In 1970, Intel Corporation introduced the first dynamic RAM. Its density (capacity) was 1024 bits and it used a capacitor to store each bit. The use of a capacitor as a means to store data cuts down the number of transistors needed to build the cell; however, it requires constant refreshing due to leakage (泄漏).The major advantages of DRAM memory are high density (capacity), cheaper cost per bit, and lower power consumption per bit.The disadvantage is that it must be refreshed periodically, due to the fact that the capacitor cell loses its charge; furthermore, while it is being refreshed, the data cannot be accessed.After the 1K-bit chip came the 4K-bit in 1973, and then the 16K chip in 1976. The 1980s saw the introduction of 64K, 256K, and finally 1M and 4M memory chip. The 1990s saw the 16M, 64M, and 256M DRAM chip.图 65 256Kx1 DRAM6.2 MEMORY ADDRESSING DECODINGCurrent system designs use CPLDs (complex programmable logic devices), in which memory and address decoding circuitry are integrated into one programmable chip. However it is important to understand how this task can be performed with common logic gates.6.2.1 Simple logic gates as address decoderIn connecting a memory chip to the CPU, the data bus is connected directly to the data pins of the memory.Control signals MEMR and MEMW are connected to the OE and WR pins of the memory chip, respectively.In the case of the address buses, while the lower bits of the address go directly to the memory chip address pins, the upper ones are used to activate the CS (sometimes the chip select is also referred to as a chip enable (CE) pin of the memory chip. It is the CS pin along with RD/WR that allows the flow of data in or out of the memory chip.The CS input is active low and can be activated using some simple logic gates, such as NAND and inverters.图 66 Using simple logic gates as decoder图 67 Decoder and its associated address range6.2.2 Using the 74LS138 as decoder图 68 74LS138 decoderThe 3 inputs A, B, and C of the 74LS138 generate 8 active-low outputs Y0-Y7. Each Y output is connected to the CS of a memory chip, allowing control of 8 memory blocks by a single 74LS138.G2A, G2B, and G1 can be used for address or control signal selection., Notice that G2A and G2B are both active low, while G1 is active high. If any one of the inputs G1, G2A, and G2B is not connected, they must be activated permanently by either Vcc or ground, depending on the activation level.图 69 74LS138 as decoderExample:Looking at the design in the following figure, find the address range for (a) Y4, (b) Y2, and (c) Y7, and verify the block size controlled by each Y.图 610 74LS138 as decoderSolution:(a) The address range for Y4 is calculated as follows:A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A01111000000000000000011110011111111111111The above shows that the range for Y4 is F0000H to F3FFFH.Notice that A19, A18, and A17 must be 1 for the decoder to be activated. Y4 will be selected when A16, A15 and A14 = 100BA13-A0 will be 0 for the lowest address and 1 for the highest address.(b) The address range for Y2 is E8000H to EBFFFHA19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A01110100000000000000011101011111111111111(c) The address range for Y7 is FC000H to FFFFFHThe block size is 16K.6.3 存储器容量的扩展当使用一片ROM或RAM芯片不能满足容量要求时，需要将若干ROM或RAM组合起来。6.3.1 位扩展方式若一片ROM或RAM芯片中的字数（字节数量）已经够用，而每一个字的位数不够时，应采用位扩展的连接方式将多个ROM或RAM芯片组合成位数更多的存储器。例：用8片1024x1位的RAM连接成1024x8位的RAM。图 611 6.3.2 字扩展方式也称地址扩充。若每一片ROM或RAM芯片中的数据位数已经够用，而每一个字数不够时，应采用字扩展的连接方式将多个ROM或RAM芯片组合成位数更多的存储器。例：用4片256x8位的RAM连接成1024x8位的RAM。图 612 地址分配：（1）000H 0FFH（2）100H 1FFH（3）200H 2FFH（4）300H 3FFH6.4 存储器与CPU的连接将存储芯片的引脚与系统总线相连接。6.4.1 数据线的连接按位扩展方式将芯片扩展到数据总线宽度，形成存储器模块（内存条）。6.4.2 地址线的连接存储芯片的地址通常应全部与系统的低位地址总线相连，寻址时这部分地址的译码是在芯片内部完成的，称为“片内译码”。设某存储芯片有n根地址线，当该片被选中后，其地址线将输入n位地址，芯片内部进行n:2n的译码，译出的的地址范围为：000(n位)到111(n位)6.4.3 片选端的译码一个存储芯片（组）很难满足存储系统的要求，常利用地址扩展的方式将多个存储芯片（组）组织起来。将存储芯片的片选端与系统的高位地址线相关联，当高位地址满足一定条件时才会选中某个指定的芯片（组）。具体的方法有：l 全译码，使用系统的全部高位地址线参加对芯片（组）的译码寻址。l 部分译码，只使用系统的部分高位地址线参加对芯片（组）的译码寻址。l 线选译码，仅使用某一高位地址线选中某个芯片（组）。6.4.3.1 全译码所有系统地址线均参与对存储单元的译码寻址。低位地址线对芯片内各存储单元译码寻址，片内译码。高位地址线对芯片译码寻址，片选译码。每个存储单元的地址都是唯一的，不存在地址重复，但译码电路可能比较复杂，连线也较多。图 613该片2764的地址范围是：A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0000111000000000000001C000000111011111111111111DFFF6.4.3.2 部分译码只有部分高地址线参与片选译码。对于那些未参与译码的高地址可以为1也可以为0，因此每个存储单元将对应多个地址，造成地址重复，需要选取其中的一个可用地址。采用部分译码可以简化译码电路的设计，但是由于地址重复，系统地一部分地址空间资源被浪费。一般应安排最高地址线不参与译码。图 614芯片A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A01xx10x0000000000000001111111111112xx10x0010000000000001111111111113xx10x0100000000000001111111111114xx10x011000000000000111111