数字电路EDA技术复习资料.doc

数字电路EDA技术复习资料1. 用VHDL语言设计一个4输入同或门。library ieee;use ieee.std_logic_1164.all;entity yhm4 is port(x1,x2,x3,x4:in std_logic; y:out std_logic);end;architecture x of yhm4 isbegin y=x1 xnor x2 xnor x3 xnor x4;end;2. 在同一个VHDL文本中同时实现一个二输入的与门、或门、与非门、或非门、异或门及反相器的逻辑功能。library ieee;use ieee.std_logic_1164.all;entity ljm is port(a,b:in std_logic; yand,yor,ynot,ynor,ynand,yxor:out std_logic);end;architecture x of ljm isbegin yand=a and b; yor=a or b; ynot=not a; ynor=a nor b; ynand=a nand b; yxor= a xor b;end;3. 用VHDL设计一个实现三输入端的多数表决器。library ieee;use ieee.std_logic_1164.all;entity bjq3 is port(a,b,c:in std_logic; y:out std_logic);end;architecture x of bjq3 is signal ty:std_logic_vector(2 downto 0);begin ty=a&b&c; with ty select y=0 when 000, 0 when 001, 0 when 010, 1 when 011, 0 when 100, 1 when 101, 1 when 110, 1 when 111, X when others;end;4. 用并行信号赋值语句设计8选1数据选择器。library ieee;use ieee.std_logic_1164.all;entity xzq8 is port(x:in std_logic_vector(7 downto 0); sel:in std_logic_vector(2 downto 0); f:out std_logic);end;architecture a of xzq8 isbegin f=x(0) when sel=000 else x(1) when sel=001 else x(2) when sel=010 else x(3) when sel=011 else x(4) when sel=100 else x(5) when sel=101 else x(6) when sel=110 else x(7) when sel=111 else X;end;5. 分别用IF语句和CASE语句设计3-8译码器。1）IF语句2）CASE语句library ieee;use ieee.std_logic_1164.all;entity de38 is port(x:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0);end;architecture a of de38 isbegin process(x) begin if x=000 then y=00000001; elsif x=001 then y=00000010; elsif x=010 then y=00000100; elsif x=011 then y=00001000; elsif x=100 then y=00010000; elsif x=101 then y=00100000; elsif x=110 then y=01000000; elsif x=111 then y=10000000; else yyyyyyyyyy=XXXXXXXX; end case; end process;end;6. 分别用IF语句和条件信号赋值语句实现8-3线优先编码器（输入、输出低电平有效）。1）IF语句2）条件信号赋值语句library ieee;use ieee.std_logic_1164.all;entity bmq is port(x:in std_logic_vector(7 downto 0); y:out std_logic_vector(2 downto 0);end;architecture a of bmq isbegin process(x) begin if x(7)=0 then y=000; elsif x(6)=0 then y=001; elsif x(5)=0 then y=010; elsif x(4)=0 then y=011; elsif x(3)=0 then y=100; elsif x(2)=0 then y=101; elsif x(1)=0 then y=110; elsif x(0)=0 then y=111; else y=XXX; end if; end process;end;library ieee;use ieee.std_logic_1164.all;entity bmq_2 is port(x:in std_logic_vector(7 downto 0); y:out std_logic_vector(2 downto 0);end;architecture a of bmq_2 isbegin y=000 when x(7)=0 else 001 when x(6)=0 else 010 when x(5)=0 else 011 when x(4)=0 else 100 when x(3)=0 else 101 when x(2)=0 else 110 when x(1)=0 else 111 when x(0)=0 else XXX;end;7. 用数据流描述方法，编写8位全加器的VHDL源代码。library ieee;use ieee.std_logic_1164.all;entity qjq8 is port(a,b:in std_logic_vector(8 downto 1); cin:in std_logic; s :out std_logic_vector(8 downto 1); c :buffer std_logic_vector(8 downto 0);end;architecture behave of qjq8 isbegin process(a,b,cin) begin c(0)=cin; for i in 1 to 8 loop s(i)=a(i) xor b(i) xor c(i-1); c(i)b then y=010; elsif a=b then y=100; else y=001; end if; end process;end;9. 设计一个8位偶校验电路（输出高电平有效）。library ieee;use ieee.std_logic_1164.all;entity oxy is port(a:in std_logic_vector(7 downto 0); y:out std_logic);end;architecture behave of oxy isbegin process(a) variable temp:std_logic; begin temp:=0; for i in 0 to 7 loop temp:=temp xor a(i); end loop; y=not temp; end process;end;10. 设计一个带异步复位置位功能的D触发器。 library ieee;use ieee.std_logic_1164.all;entity d_ff is port(clk,reset,d,set:in std_logic; q,qb:out std_logic);end;architecture behave of d_ff isbegin process(clk) begin if set=1 and reset=0 then q=0;qb=1; elsif reset=1 and set=0 then q=1;qb=0; elsif(clkevent and clk=1) then -rising_edge(clk) q=d;qb=not d; end if; end process;end;11. 设计一个同步T触发器。library ieee;use ieee.std_logic_1164.all;entity t_ff is port(clk,t,reset:in std_logic; q:out std_logic);end;architecture behave of t_ff is signal temp_q:std_logic;begin process(clk) begin if(clkevent and clk=1) then -rising_edge(clk) if reset=0 then temp_q=0; elsif t=1 then temp_q=not temp_q; else temp_q=temp_q; end if; end if; q=temp_q; end process;end;12. 用PROCESS语句描述带同步复位的JK触发器。library ieee;use ieee.std_logic_1164.all;entity jk_ff is port(clk,reset,j,k:in std_logic; q,qb:out std_logic);end;architecture behave of jk_ff is signal tq,tqb:std_logic;begin q=tq;qb=tqb; process(clk,reset) begin if (clkevent and clk=1) then if (reset=0) then tq=0;tqb=1; elsif (j=0)and(k=0) then tq=tq;tqb=tqb; elsif (j=0)and(k=1) then tq=0;tqb=1; elsif (j=1)and(k=0) then tq=1;tqb=0; elsif (j=1)and(k=1) then tq=not tq;tqb=not tqb; end if; end if; end process;end; 13. 设计一个16位锁存器。library ieee;use ieee.std_logic_1164.all;entity keep is port(g,ce:in std_logic; din:in std_logic_vector(15 downto 0); q:out std_logic_vector(15 downto 0);end;architecture behave of keep is signal temp_q:std_logic_vector(15 downto 0);beginp1:process(din,g) begin if(g=1) then temp_q=din; else temp_q=temp_q; end if; end process;p2:process(ce,temp_q) begin if(ce=0) then q=temp_q; else q=ZZZZZZZZ; end if; end process;end;14. 用VHDL设计实现216任意进制异步可逆计数器。library ieee;use ieee.std_logic_1164.all;entity knjsq is port(clk,reset,updn:in std_logic; d:in integer range 1 to 15; q:out integer range 0 to 15);end;architecture behave of knjsq isbegin process(clk,reset) variable temp_q:integer range 0 to 15; begin if(reset=0)then temp_q:=0; elsif(clkevent and clk=1) then if(updn=1)then if temp_q=d then temp_q:=0; else temp_q:=temp_q+1; end if; else if temp_q=0 then temp_q:=d; else temp_q:=temp_q-1; end if; end if;end if; q=temp_q; end process;end;15. 用VHDL设计实现输出占空比为30%的20分频器。library ieee;use ieee.std_logic_1164.all;entity fpq20 is port(clk :in std_logic; fout:out std_logic);end;architecture behave of fpq20 is signal temp_f:std_logic; signal tout :integer range 0 to 19;beginx1:process(clk) begin if (clkevent and clk=1) then if tout=19 then tout=0; else tout=tout+1; end if; end if; end process;x2:process(tout) begin if (tout14) then temp_f=0; else temp_f=1; end if; fout=temp_f; end process;end;16. 用VHDL语言设计一个输出为矩形波信号的分频器，分频系数为9，令该分频器的时钟信号