嵌入式系统架构软体设计 - 德霖技術學院資訊工程系.pptVIP

嵌入式系统架构软体设计,嵌入式系統架構軟體設計 -using ARM Day #3,#4,#5 Modules Outline,課程介紹,Day #3 Simple RISC Assembly Language ARM Assembly Language ARM Development Suite 使用練習 Day #4 Arm Instruction set Important ASM Programming Skills ARM/THUMB/C Interworking Day #5 ARM Exception Handler Build ARM ROM Image Use NET-Start! ucLinux BSP,嵌入式系統產品設計流程概觀,Steve Furber, ARM system-on-chip Architecture, 2nd ed. Seal, ARM architecture reference manual, 2nd ed. ARM Development Suite-Getting Started ARM Development Suite-Developer Guide ARM Development Suite-Assembler Guide / 2002嵌入式系統開發經驗 Building powerful platform with Windows CE Software Engineering, A practitioners Approach 3rd ed. Professional Symbian Programming,嵌入式系統架構軟體設計 -using ARM Module #3-1: Simple RISC Assembly Concept,RISC精简指令集vs.CISC复杂指令集,Hardware instruction decode logic Pipeline execution Single -cycle execution,Large microcode ROMs to decode instruction Allow little pipeline Many cycles to completer a single instruction,A smaller die size A shorter development time A higher performance Poor code density,MUO 一個簡單的處理器,MUO指令集與資料路徑,指令規則,指令執行範例,ADD 0x16A ACC:=ACC+mem0x16A,運算範例,C function: Main() C=A+B; ,MUO 機器指令 LDA 0x100 ADD 0x104 STO 0x108,練習： MUO微處理器的運算,0x000 LDA 0x100 0x002 SUB 0x104 0x004 STO 0x100 0x006 JNE 0x000 0x008 STP,請描述此段程式的動作，暫存器值的變化、與資料流。請用C語言來寫出這段程式碼。,嵌入式系統架構軟體設計 -using ARM Module #3-2: ARM Assembly Language,ARM7TDMI資料流,e.g.r3:=r4+(r4,2) ADD r3,r4,r4,LSL#2 A bus B bus,ARM 的暫存器,30 general-purpose, 32 bits registers 1 Program Counter (PC) 1 Current Program Status Register (CPSR) 5 Saved Program Status Registers (SPSR),User mode FIQ mode irq mode SVC mode abort mode undefined mode,r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13 (sp),r14 (lr),r15 (pc),cpsr,Program Status Register,CPSR: Current Program Status Register SPSR: Saved Program Status Register,Condition code flags N: Negative result from ALU Z: Zero result from ALU C: ALU operation Carried out V: ALU operation overflowed,Interrupt Disable bits I: disable the IRQ F: Disable the FIQ,T bit Architecture xT only T=0: ARM state T=1: Thumb state,Q: Sticky Overflow flag Architecture 5TE only QADD, QSUB,J: Processor in Jazelle state Architecture 5TEJ only,Mode bits Specify the processor mode 10000 User 10001 FIQ 10010 IRQ 10011 SVC 10111 Abort 11011 Undef 11111 System,31 30 29 28 27 24 7 6 5 4 0 N Z C V Q J undefined I F T mode,Program Counter R15,ARM state: All ARM instructions are four bytes long (one 32-bit word) and are always aligned on a word boundary. The PC value is stored in bits 31:2 with bits 1:0 undefined. In Thumb state: All instructions are 16 bits wide, and halfword aligned The PC value is stored in bits31:1 with bits 0 undefined. In Jazelle state: All instructions are 8 bits wide. The processor performs a word access to read 4 instructions at once.,Link Register R14,Register 14 is the Link Register (LR). This register holds the address of the next instruction after a Branch and Link (BL) instruction, which is the instruction used to make a subroutine call. At all other times, R14 can be used as a general-purpose register,Other Register R0-R13,The remaining 15 registers have no special hardware purpose. Their uses are defined purely by software. By convention, ARM assembly language use R13 as Stack Pointer. C and C+ compilers always use R14 as the Stack Pointer(SP).,Structure of ARM Assembly Language Module,AREA Sectionname,attr,attr Start of New code or data section. CODE: contain machine instructions. READONLY: section should not be written to. Other attr: DATA, NOINIT, READWRITE, Declares an entry point to a program. Labels. Declares the end of the source file.,Calling Subroutines Uses BL,BL destination destination is the label on the first instruction of the subroutine. BL does: place the return address in the link register (R14) sets PC to the address of the subroutine. In the subroutine we can use “MOV pc,lr” to return. By convention, R0-R3 are used to pass parameters.,Calling Subroutines Example,; name this block of code ; mark first instruction ; to execute,; Set up parameters ; Call subroutine,; angel_SWI reason_report Exception ; ADP_Stopped_ApplicationExit ; ARM semihosting SWI,; Subroutine code ; Return from subroutine. ; Mark end of file,Constant Data Types,Numbers Numeric constants are accepted in three forms: Decimal, for example, 123 Hexadecimal, for example, 0x7B n_XXX where: n is as base between 2 and 9 xxx is a number in that base. Boolean TRUE and FALSE must be written as TRUE and FALSE. Characters constants consist of opening and closing single quotes X, enclosing either a single character or an escaped character, using the standard C escape characters. Strings consist of opening and closing double quotes “XXXX”. If double quotes or dollar signs are used within a string as literal text characters, they must be represented by a pair of the appropriate character. For example, you must use $ if you require a single $ in the string. The standard C escape sequences can be used within string constants.,Almost all ARM instructions can be conditionally executed. e.g. ADDS r0, r1, r2 ADDEQ r0, r1, r2 Execute if the N, Z, C and V flags in the CPSR satisfy a condition specified in the instruction, otherwise, NOP.,Conditional ARM Instructions,XXXCC,Almost every ARM instruction can be executed conditionally on the state of the ALU state flags in the CPSR. Add an S suffix to an ARM data processing instruction to make it update the ALU state flags in the CPSR E.g. ADDS r0, r1, r2 ; r0= r1+ r2 and update ALU status in CPSR. In ARM state, you can: update the ALU status flags in the PSR on the result of a data operation execute several other data operation without updating the flags execute following instructions or not, according to the state of the flags updated in the first operation. In Thumb state most data operations always update the flags and conditional execution can only be achieved using the conditional branch instruction (B). Do not use the S suffix with CMP, CMN, TST, or TEQ. These comparison instructions always update the flags.,Conditional Execution,ALU Status Register in CPSR,N Set when the result of the operation was Negative. Z Set when the result of the operation was Zero. C when the result of the operation was Carry. A carry occurs if the result of an addition is greater than or equal to 232 If the result of a instruction is positive, or as the result of an inline barrel shifter operation in a move or logical instruction. V Set when the operation caused oVerflow. Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than 231. Q ARM architecture v5Eonly. Sticky flag. Used to detect saturation in special saturating arithmetic instructions (e.g. QAD, ASUB, QDADD, and QDSUB), Or overflow in certain multiply instructions (SMLAxy and SMLAWy),Conditional Code Suffixes,Conditional Code Examples,ADD r0, r1, r2 ;r0 = r1 + r2, dont update flags ADDS r0, r1, r2 ;r0 = r1 + r2, and update flags ADDCSS r0, r1, r2 ;if C flag set then r0 = r1 + r2, and update flags CMP r0, r1 ;update flags based on r0-r1. Example code sequence: MOV R0, #0 LOOP ADD R0, R0, #1 CMP R0, #10 BNE LOOP SUB R1, R1, R0,Write Efficient and small size Code by Conditional Instruction,Exercise,Write program by ARM assembly, & evaluate the execution cost in clock. A Branch needs 3 cycles, others cost 1.,註：唯需透過CMP, SUB, B這三個指令，加上條件式， 就可以完成。,While (r1!=r2) do if (r1r2) r1=r1-r2; else r2=r2-r1; ,嵌入式系統架構軟體設計 -using ARM Module #3-3: ARM Development Suite使用練習,ARM ADS 1.2,Others: C & C+ Libraries ARM firmware suite AM application library RealMonitor: for real time debug monitor,Implementation Integration by command line, makefile, CodeWarrior,Pre-configured Project Stationary Files,Debug This build target is configured to built output binaries that are fully debuggable, at the expense of optimization. Release This build target is configured to output binaries that are fully optimized, at the expense of debug information. DebugRel This build target is configured to build output binaries that provide adequate optimization, and give a good debug view.,Possible Development Environments,Reference,ARM Developer Suite Version 1.2 Getting Started 請依Chapter 3練習使用ADS。,嵌入式系統架構軟體設計 -using ARM Module #3-4: ARM Instruction Set,ARM 指令集特點,所有指令為32 bits ADD r0, r1, r2; r0:=r1+r2 大部分的指令，可以在一個週期內執行完成 指令皆可為有條件式執行 Load/store架構,Thumb指令集,Thumb指令長度為16 bits 針對程式碼的密度最佳化， 約為65%的ARM code size 適合小記憶體系統 Thumb指令支援的功能為ARM指令集的一部分 執行期間必須切換到Thumb模式 ADDS r1,r1,#3 ADD r1,#3,Jazelle,Jazelle技術可以讓ARM執行8-bit Java Bytecode 硬體可以支援到95%的bytecodes 速度約為一般軟體JVM的五倍,ARM指令集分類,Branch instructions Data-processing instructions Load and store instructions Status register transfer instructions Coprocessor instructions Exception-generating instructions.,Branch Instructions,B Branch BL Branch with link Store the return address to r14 e.g. CMP r2, #0 BLEQ function function MOV PC, r14,Branch Instruction Encoding,The range of the branch instruction is +/- 32 Mbytes L: the branch and link variant.,Assembly Format: BLS Rm BLS ,Branch instructions example,e.g. C if (a=0) function 1 (1); Else c function 1() function2(); function2() return;,ASM function 1 STMFD r13!, r0-r4, r14 BL function2 LDMFD r13!, r0-r4, pc function2 MOV pc, r14,Data-processing Instructions Encoding,Assembly Format: S Rd, Rn,# S Rd, Rn,Rm, shift,Data Processing Opcode,Assembly Format: S Rd, Rn # S Rd, Rn, Rm, Opcode Mnemonic Meaning Effect 24:21 0000 AND Logical bit-wise AND Rd:=Rn & Op2 0001 EOR Logical bit-wise excusive OR Rd:=Rn EOR Op2 0010 SUB Subtract Rd:=Rn-Op2 0011 RSB Reverse subtract Rd:=Op2-Rn 0100 ADD Add Rd:=Rn+Op2 0101 ADC Add with carry Rd:=Rn+Op2+C 0110 SBC Subtract with carry Rd:=Rn-Op2+C-1 0111 RSC Reverse subtract with carry Rd:= Op2-Rn+C-1 1000 TST Test Scc on Rn&Op2 1001 TEQ Test equivalence Scc on Rn EOR Op2 1010 CMP Compare Scc on Rn-Op2 1011 CMN Compare negated Scc on Rn+Op2 1100 ORR Logical bit-wise OR Rd:=Rn | Op2 1101 MOV Move Rd:=Op2 1110 BIC Bit clear Rd:=Rn AND NOT Op2 1111 MVN Move negated Rd:=NOT Op2,Example Data-processing Instructions,Arithmetic operations ADD r0,r1,r2 ; r0=r1+r2 SUB r0,r1,r2 ; r0=r1-r2 RSB r0,r1,r2 ; r0=r2-r1 Bit-wise logical operations AND r0,r1,r2 ; r0 = r1 bit clear,Example Data-processing Instructions (cont.),Register movement operations MOV r0,r2 ; r0=r2 MVN r0,r2 ; r0=not r2 Comparison operations (set condition code bits N, Z, C, V) CMP r1,r2 ; set cc on r1-r2 Immediate operands ADD r3,r3,#1 ; r3=r3+1 AND r8,r7, # r8=r77:0 & : base 16,Shifter,LSL: Logical Left Shift (X2) LSR: Logical Shift Right (/2) ASR: Arithmetic Right Shift ROR: Rotate Right,Shifter Applications,e.g. #1 ADD r3,r2,r1, LSL #3; r3:= r2+8*r1 e.g. #2 r0=r1*5 r0=r1+(r1*4) ADD r0 ,r1, r1, LSL #2,Multiply Instruction Binary Encoding,Assembly Format MULS Rd, Rm, Rs MLAS Rd, Rm, Rs, Rn S RdHi, RdLo, Rm, Rs RdHi: the most significant 32 bits of 64-bit format number RdLo: the least significant 32 bits of 64-bit format number Opcode Mnemonic Meaning Effect 23:21 000 MUL Multiply (32-bit result) Rd:=(Rm*Rs)31:0 001 MLA Multiply-accumulate (32-bit result) Rd:=(Rm*Rs+Rn)31:0 100 UMULL Unsigned multiply long RdHi:RdLo:=Rm*Rs 101 UMLAL Unsigned multiply-accumulate long RdHi:RdLo+=Rm*Rs 110 SMULL Signed multiply long RdHi:RdLo:=Rm*Rs 111 SMLAL Signed multiply-accumulate long RdHi:RdLo+=Rm*Rs,Assembly Format: CLZS Rd, Rm Sets Rd to the number of the bit position of the most significant 1 in Rm. If Rm=0 Rd=32. E.g. MOV r0, #&100 CLZ r1, R0 r1=8,Count Leading Zeros Instruction (v5T only),練習,用ARM Assembly寫一個程式，包含一個subroutine用來做x10的運算。 用ADS環境。 不支援具有乘法器功能的ARM Core 。 main() x=5; y=mul_ten(x); int mul_ten(x) return 10*x; ,Single Word and Unsigned Byte Data Transfer Instruction Binary Encoding,Assemble Format: LDR|STRB Rd,Rn, ! ; Pre-indexed form LDR|STRB Rd,Rn, ; Post-indexed form LDR|STRB Rd,LABEL ; PC-relative form,Load and Store Examples,Single register load and store LDR r0, r1 ; r0 := mem32r1 STR r0, r1 ; mem32r1 := r0 Base plus offset addressing Pre-indexing LDR r0, r1, #4 ; r0 := mem32r1+4 Auto indexing LDR r0, r1, #4! ; r0 := mem32r1+4, r1=r1+4 Post-indexed LDR r0, r1, #4 ; r0 := mem32r1, r1=r1+4 PC-relative LDR r1, UART_ADD ; UART address into r1 STRB r0, r1 ; store data to UART UART_ADD address literal,Half-word and Signed Byte Data Transfer Instruction Binary Encoding,Assemble Format: LDR|STRH |SH|SB Rd;Rn, ! ; Pre-indexed form LDR|STRH |SH|SB Rd;Rn, ; Post-indexed form, An unsigned value is zero-extended to 32 bits when loaded; A singed value is extended to 32 bits by replicating the most significant bit of the data.,Half-word Load/Store Example,ADR r1, ARRAY1 ; half-word array start ADR r2, ARRAY2 ; word array start ADR r3, ENDARR1 ; ARRAY1 end +2 LOOP LDRSH r0, r1, #2 ; get signed half-word STR r0, r2, #4 ; save word CMP r1, r3 ; check for end of array BLT LOOP ; if not finished, loop,練習：字串複製,寫一個Assembly程式做字串複製的動作。 用ADS環境。 A=“Hello, this is a sunny day!” B=“ ”,Multiple Register Data Transfer Instruction Binary Encoding,In a non-user mode, CPSP may be restored by: LDM| Rn!, Full or empty: The stack pointer can either point to the last item in the stack (a full stack), or the next free space on the stack (an empty stack).,Assembly Format: LDM|STM Rn!, , IA: Increment after. IB: Increment before. DA: Decrement after. DB: Decrement before.,Example Addressing Mode for LDM/STM,ISR Example,e.g. Interrupt handler _irq void IRQHandler(void) volatile unsigned int *base=(unsigned int *) 0x80000000; If (*base=1) C_int_handler_1( ); *(base+1)=0; ,IRQHandler PROC STMFD spl,r0-r4, r12, lr MOV r4,#0x80000000 LDR r0, r4,#0 SUB sp,sp,#4 CMP r0,#1 BLEQ C_int_handler MOV r0,#0 STR r0,r4,#4 ADD sp, sp, #4 LDMFD spl,r0-r4, r12, lr SUBS pc, lr, #4,Swap Memory and Register Instruction Binary Encoding,Assembly Format: SWPB Rd,Rm,Rn,SWP Example,ADR r0, SEMAPHORE SWPB r1, r1, r0 ; exchange byte r0,r1,r?,0,Status Register to General Register Transfer Instruction Binary Encoding,Assembly Format: MRS Rd,CPSR|SPSR,E.g. MRS r0, CPSR ; move the CPSR to r0 MRS r3, CPSR ; move the SPSR to r3 Note: The SPSR form should not be used in user or system mode.,Transfer to Status Register Instruction Binary Encoding,Assembly Format: MRS CPSR_f|SPSR_f, # MRS CPSR_|SPSR_, Rm, C - the control field PSR7:0 X the extension field PSR15:8 S the status field PSR23:16 F the flags field PSR31:24,MSR Example,Set N, C,V, Z flags: MSR CPSR_f, # set bit 29 of r0 MSR CPSR_f, r0 : move back to CRSR,練習：切換ARM操作模式,寫一段程式，將ARM由Supervisory mode切換到IRQ mode。 用ADS環境。 31 30 29 28 27 24 7 6 5 4 0 N Z C V Q J undefined I F T mode,Mode bits Specify the processor mode 10000 User 10001 FIQ 10010 IRQ 10011 SVC 10111 Abort 11011 Undef 11111 System,Coprocessor Instructions,There are 3 types: Coprocessor data operations CDP: initiate a coprocessor data processing operation Coprocessor Register transfers MRC: Move to ARM register from coprocessor register MCR: Move to coprocessor register from ARM register Coprocessor Memory transfer LDC: load coprocessor register from memory STC: store from coprocessor register to memory,Exception-generating & Semaphore Instructions,SWI Used to cause a Software Interrupt exception to occur SWI SWI 0x123456 BKPT Used from software breakpoints in ARM architecture 5 or above. Cause a Prefetch Abort exception to occur. BKPT ,Summary of ARM Architectures,Core Architecture ARM1 v1 ARM2 v2 ARM2as, ARM3 v2a ARM6, ARM600, ARM610 v3 ARM7, ARM700, ARM710 v3 ARM7TDMI, ARM710T, ARM720T, ARM740T v4T StrongARM, ARM8, ARM810 v4 ARM9TDMI, ARM920T, ARM940T v4T ARM9ES, XScale Microarchitecture v5TE ARM10TDMI, ARM1020E v5TE 926EJ-S/1026EJ-S v5TEJ,Reference,S. Furber, ARM system-on-chip Architecture, 2nd ed. Addison-Wesley Seal. ARM architecture reference manual, 2nd ed. Addison-Wesley ARM Development Suite User Guide,嵌入式系統架構軟體設計 - using ARM Module #3-5: Important ARM ASM Programming Skills,Load Constant into Register,Direct loading with MOV and MVN Loading with LDR Rd,=const,Direct Load Constant into Register,MovcondS,Operand2 Load immediate constant to register E.g. MOV R1,0x18 ;R1=0x18 Can load any 8-bit constant, giving a range of 0x00 to 0xFF MVN: load the bitwise complement of these values. The numerical values are (n+1).,Compiler ERROR MSG: Immediate n out of range for this operation.,224,Loading with LDR Rd,=const,The LDR Rd,=const pseudo-instruction can construct any 32-bit numeric constant in a single instruction The LDR pseudo-instruction generates the most efficient code for a specific constant: If the constant can be constructed with a MOV or MVN instruction, the assembler generates the appropriate instruction. If the constant cannot be constructed with a MOV or MVN instruction, the assembler: Places the value in a literal pool. Generates an LDR instruction with a program-relative address that reads the constant from the literal pool. e.g.: LDR Rn,pc,#offset to literal pool ;load register n with one word from the address pc+offset Literal Pool: A portion of memory embedded in the code to hold constant values.,LDR & Literal Pool Example,; ; c:ARMADSv1_2Examplesasmloadcon.s AREA Loadcon, CODE, READONLY ENTRY START BL func1 BL func2 stop MOV r0,#0x18 ; =MOV R0, #42 LDR r1, =0x20026 SWI 0x123456 func1 LDR r0, =42 ; =MOV R0, #42 LDR r1, =0x55555555 ; =LDR R1, PC, #offset to Literal