《状态机与数据路径》PPT课件.ppt

6.4.2 状态机与数据路径,数据通道结构,FSMD系统结构,S=S0,S1,S2,Sl 表示状态集合； I =i0，i1，i2，,im 表示输入集合； O=o0,o1,o2,.,on 表示输出集合； V=v0,v1,v2,.,vn 表示变量集合； F：SIVS 表示映射某种集合到某一状态的瞬态函数； H：SO+V 表示当前状态映射到输出或变量的激活函数； S0是初始状态。,研究目标,1. 资源约束: 硬件功能单元 如：算数单元 (abs, max, min, +, -) 移位器 2.时间约束: 时序约束 如：有限状态机状态数量，流水线结构,时间调度与分配,数据流结构 X=a(axb)+(cxd)+d 数据流向图 把计算表达式转化为计算路径的方法 同步结构：任何时刻只能保存一个数值； 异步结构：每条线对应数据队列，数据进出队列与节点的数据处理是异步操作。,数据流,X=a(axb)+(cxd)+d,调度算法 (1/7),调度算法 (2/7),ASAP（as soon as possible ）： 假设每一操作要在一个时钟内精确执行。 在每一个状态内，功能单元和资源是可变的。 执行的操作都是可变的。 ALAP( as late as possible)： 如果计算路径保持到最终的计算步骤，则操作在最后可能的状态内执行，,ASAP,ALAP（time constraint is 4）,调度算法 (3/7),mobility,Scheduling: 资源约束 One multiplier and two adders,调度算法(4/7),功能单元分配： Multi(*) adder(+1) adder(+2) S_1 op1 op5 S_2 op7 op2 S_3 op3 S_4 op6 op4 S_5 op8,资源分配：,调度算法 (5/7),寄存器分配 (lifetime of each operand),需要 7 registers,调度算法 (6/7),Left edge algorithm R1:a, t3, t4 R2:b, t2, t7 R3:c, t6 R4:d R5:e R6:t1 R7:t5,调度算法 (7/7),. . . .,Datapath 优化,1. Resource optimization (a) 存储共享 (b) 功能单元共享 (c) 总线共享 (d) 寄存器合并 2. Time optimization (a) 连接或多循环 (b) 功能单元 pipelining (c) 数据路径 pipelining (d) 控制路径 pipelining,连接与多循环操作,连接允许在同一状态中执行两个以上操作的串行执行。 连接减少状态数并增加功能。 多循环操作允许一个操作在两个以上时钟周期执行操作。 多循环操作减小功能单元的尺寸。 连接与多循环操作常常被用在非关键路径以提高资源利用率和功能。,交通信号控制器 (1/7),Control Unit,Datapath,Counter,Comparator,Red,Green,Yellow,Next State Logic,Output Logic,State Registers,Seq.,Comb.,Comb.,Recount_counter,R,Y,G,1/100,1/010,1/001,0/100,0/010,0/001,Recount_Counter16/Red Green Yellow,Input/Output,Rt Gt Yt,Current_times,Recount_counter,4 2 0,R_time: 4+1=5 cycles G_time: 2+1=3 cycles Y_time: 0+1=1 cycles,Traffic Light Controller (2/7),module traffic(Clock,Reset,Red,Green,Yellow); input Clock,Reset; output Red,Green,Yellow; wire Recount_conter; wire 3:0 Counter_Number; Traffic_Control (.Clock(Clock),.Reset(Reset), .Recount_Counter16(Recount_conter),.Red(Red), .Green(Green),.Yellow(Yellow); Datapath (.Clock(Clock), .Reset(Reset), .RGY(Red,Green,Yellow), .Recount(Recount_conter); endmodule,module Datapath(Clock, Reset, RGY, Recount); input Clock, Reset; input 2:0 RGY; output Recount; wire 3:0 Counter_Number; Compare A1(.current_times(Counter_Number), .RGY(RGY), .Recount_conter16(Recount); Counter16 A2(.Clock(Clock),.Reset(Reset), .Recount_Counter16(Recount),.Count_Out(Counter_Number); endmodule,Traffic Light Controller (3/7),module Counter16(Clock,Reset,Recount_Counter16, Count_Out); input Clock,Reset,Recount_Counter16; output 3:0 Count_Out; reg 3:0 Count_Out; always(posedge Clock) begin if(Reset) Count_Out=0; else begin if(Recount_Counter16) Count_Out=0; else Count_Out=Count_Out+1; end end endmodule,Traffic Light Controller (4/7),module compare(current_times, RGY, Recount_conter16); input 2:0 RGY; input 3:0 current_times; output Recount_conter16; reg Recount_conter16; parameter R_times=4, G_times=2, Y_times=0; always (RGY) begin case(RGY) 3b100:begin if(current_times =R_times) Recount_conter16=1; else Recount_conter16=0; end,3b001:begin if(current_times =Y_times) Recount_conter16=1; else Recount_conter16=0; end 3b010:begin if(current_times =G_times) Recount_conter16=1; else Recount_conter16=0; end default: Recount_conter16=1; endcase end endmodule,Traffic Light Controller (5/7),State Register (Seq. C.),Next State Logic (Comb. C.),module Traffic_Control(Clock,Reset, Recount_Counter16,Red,Green,Yellow); input Clock, Reset,Recount_Counter16; output Red, Green, Yellow; reg Red, Green, Yellow; reg 1:0 currentstate,nextstate; parameter 1:0 Red_Light=0, Green_Light=1, Yellow_Light=2; always(posedge Clock) begin if(Reset) currentstate = Red_Light; else currentstate = nextstate; end,always(currentstate) begin case(currentstate) Red_Light:begin if(Recount_Counter16) nextstate=Green_Light; else nextstate=Red_Light; end Green_Light:begin if(Recount_Counter16) nextstate=Yellow_Light; else nextstate=Green_Light; end Yellow_Light:begin if(Recount_Counter16) nextstate=Red_Light; else nextstate=Yellow_Light; end default: nextstate=Red_Light; endcase end,Traffic Light Controller (6/7),Output Logic (Comb. C.),always (currentstate) begin case(currentstate) Red_Light:begin Red=1b1; Green=1b0; Yellow=1b0; end Green_Light:begin Red=1b0; Green=1b1; Yellow=1b0; end Yellow_Light:begin Red=1b0; Green=1b0; Yellow=1b1; end,default:begin Red=1b0; Green=1b0; Yellow=1b0; end endcase end endmodule,Traffic Light