外文翻译(同名7836).doc

可选（在打印前须删除）2014届本科毕业设计(论文)外文文献翻译学 院： 物理与电子工程学院 专 业： 电子信息工程 姓 名： 学 号： (用外文写)外文出处： Web of Science 附 件： 1.外文资料翻译译文；2.外文原文。附件1：外文资料翻译译文基于ARM应用集成系统的基准测试I.引言一个完整的处理器和微处理器之间的界限一直是一个相当主观的。随后，比起ARM应用处理器，只有少数技术跨越条线。这些强大的的微处理器几乎存在于每一个移动手持设备的主体，（他们）能够运行完整的操作系统，同时仍然保持嵌入式低功耗优势。由于这些应用处理器变得更加成熟，随后基于他们（设计）的设备变得功能更加强大，他们变得更加难以被定义。随着这些设备的发展演变，它们将继续成为一个自成独特一类，因此，显而易见，它们应该被视为自己独特的一类。这些应用的处理器绝大多数采用了ARM指令集架构（ISA）2。 ARM是用在各种不同的嵌入式系统，从高端应用处理器到低端微控制器。这一指令集由ARM指令集的早期版本发展而来，是ARM控股有限公司知识产权，该公司已经使用了几十年的时间发展和推广这一架构。这产生了许多的创新，导致了ARM指令集与其它嵌入式指令集进一步分化。ARM并不制造自己的处理器，取而代之的是，它们的授权IP核给其他公司，允许他们根据自身需求来修改这一技术。这种安排导致了数百的公司每年生产数十亿的ARM处理器3 4 5。许可和制造一个精确复制的处理器内核足以满足一个复杂的设计需求是很少有的。因此，被授权方经常修改内核、封装或其他组件,或都做修改。减少空间的封装技术能够被运用在整个系统电路板的每一个地方。使用不同的方法来包装系统组件，使之集成在一起,对于本论文都应当被称为集成系统678。这些集成系统具有能力强大、功能丰富和复杂的特点。很明显,许多这些集成系统设计者是直接的竞争对手。显而易见,就像选择其他处理器选项一样，能够比较和区分相近设计目的的集成系统是很重要的。虽然存在大量的基准测试,嵌入式系统和完整的处理器,甚至一些应用程序处理器都有基准测试,但是找到一个包含在一个单一的设备能测试整个系统的基准测试是非常困难。即使使用相同的核心和同样的设计目标,两家公司可能会有广泛不同的组件集成系统。同样,包装的组件的方法也会有差异。只是测试的核心是不够的,但整个系统作为一个整体必须为基准由于组件是分不开的。毕竟,为了这个目的,它表现为一个单一的设备。目标因为ARM处理器的流行,本文的主题是探索具体应用在市场中由ARM技术推动的集成系统的基准测试。在本文中，关于这个主题的几个问题将被回答。这些基于ARM应用的处理器与其他处理器之间是否足够不同以至于需要被单独区别对待，这个问题是尤其重要的，将在本论文中得到答案。接下来的问题是，在这些情况下，是否完整内核知识可以排除测试完整系统的必要性。接下来,确定是否能有一个可被接受的基准套件能够充分测试一个集成系统的全部功能同样重要。如果以上任何一个答案是否定的,那么需要去研究这一问题没有被解决的原因。最后考虑的是，这些设备未来将保持什么，将会扮演什么角色。贡献本文就一些贡献。收集技术包括在封装技术之内，封装技术致力于将一个系统包含一个封装中，笼罩在模糊和矛盾的术语。System-on-chip、system-in-package和package-on-package这些术语经常被用到，他们有着细微差别,有时能交互使用,而在其他研究实例中它们有着严重区别。这个概述和解释将有助于消除这种歧义和澄清“集成系统”包罗万象的定义。确定可被接受的用于集成系统的标准基准的特征是很有必要的。为此,在一个标准的测试基准的特性被简明扼要的概述。滥用测试基准也是被回顾和讨论的话题。OMAP35309的集成系统将被用基准测试套件MiBench10进行测试。运行基准测试的结果被包含在周密的的文档、图表、时间戳、和其他相关信息。基准状态的一个彻底的探索适用于目标平台(基于arm应用集成系统)应完成。这包括确定行业标准已经足够以及提供一个之前相关实验的和结果的简洁的收集。摘要竞争的基于arm的设计应用程序集成系统普遍存在足以保证自己的基准测试标准。测试只是ARM内核是不够的比较或对比的功能集成系统。此外应用终端处理器平衡正常的嵌入式处理器的优势与完整的处理器,因此基准对一个或另一个类别是不确定的和多余的。与日益增长的行业的必要性将继续攀升。第一章提供了一个项目的详细概况和论文语句。第二章重点关注项目所需的背景知识。这始于一个ARM指令集架构的详细概述从其历史和突出现代设备和体系结构的具体细节。一节臂后跟一看是什么让一个集成的系统概况的细节的一些包装技术用于整个系统包含一个足迹。接下来详细看看测试设备本身,Beagle Board,是包括在内。后台完成章概述的基准测试。第三章包括仔细检查准备Beagle Board的实验,看看选择适当的基准,基准选择的细节。在这之后,第四章细节工作的结果。这始于一个检查基准Beagle Board的结果。另一个流行的一部分这一章看的结果研究各种现有结果和比较基准系统之间的集成电路如OMAP和我。MX平台。第五章总结了论文。 II. 背景为了理解针对使用ARM指令集的集成系统的基准测试套件的必要性,必须有一个背景。正如简介中提到的,ARM被广泛许可，它的使用正在迅速扩大。这些被许可方可以使用ARM技术以不同的方式创建他们自己的系统。其中一些系统一起集成在一个芯片上或在一个封装包作为自己产品出售,因此,ARM技术和包装技术对于集成系统来说都是重要的。例如TI OMAP系列的产品，Beagle 板一个运用ARM OMAP处理器方便的接口,被作为基准测试的实验平台。他有强大的功能,可适应多种项目。Beagle Board也有完全开源的优势。该设备将在下文进一步探讨。基准的研究已经进行过彻底的探索,所以扩大或扩展这个话题不是本文的主要目的。然而,需要检查些什么可以为了突出缺乏适用的基准套件。它将变得清晰,有很多指标,为这些系统提供一些合适的测试。然而,没有一个基准测试是全面让人满意的。ARMARM是现在应用开发中用到的最常见的指令集之一，ARM是一个32位基于精简指令集计算机(RISC)设计策略的指令集。此体系结构的概念提出以来取得了全面的进步,扩大到多个嵌入式市场,尤其是消费电子产品。除了了解ARM的处理能力和架构外，理解ARM内核如何被广泛的发展、如何快速的取得这一水平的成功同样是重要的。历史和市场最初,ARM代表Acorn RISC机器,ARM是由英国的一家小公司的一个分支发展而来,取名为Acorn计算机有限公司,致力于进入商业计算机市场。没有任何可行的处理器选择适合他们的需求或市场的目标,所以他们选择开发一个新的架构，这一灵感来自一个由一群伯克利分校研究生证明架构开发可以在低预算和有限的设施情况下完成的RISC项目。在1985年完成ARM1主要开发项目,最终ARM2和随后的ARM3被推上市场。1990年,苹果电脑和Acorn的承包商,硅集成电路技术,辅助研究ARM下一阶段发展5。ARM在1991年第一次可嵌入RISC核心是从早期的Apple、Acorn和V-tech11共同努力的结果。ARM第一个可嵌入的核心是基于新ARMv3架构,并按照新的内核命名方案命名为ARM6。在接下来20年ARM开发了几个版本的指令集,在2004发布了Cortex 系列的ARMv7指令集。更好的视觉架构的版本如表1相关的处理器家族已经包括在内。这张表已经被简化,有各种各样的有异于这个家族的子架构版本。一些系列的指令集存在着几个架构,在该系列不同生命周期使用不同子架构。在此期间的ARM也开发了各种各样的创新让更多的芯片专门化和可选择。这虽然在这里介绍，但是在功能和扩展部分将进一步详细介绍。最显著的发展之一是Thumb,一个操作状态,它使用一个16位的压缩的ARM指令子集,可以开启或关闭。更复杂的版本的拇指,名为Thumb-2,存在于当前体系结构的家庭。拇指和Thumb-2也可以用作唯一的架构,包括常规的ARM指令集。另一个创新是Jazelle,Java执行模式用于更有效地执行Java字节码。其他更常见的,自然进步包括选项添加一个浮点单元(FPU),面向数字信号处理(DSP)的设计和多核设计。ARM Holdings作为一个知识产权授权的商业组织，将ARM IP核授权给不同的公司。这样做是代替生产和销售他们自己单一的芯片。截至2011年,ARM可以很自豪的介绍，超过150亿的ARM核已经发货,超过200家公司获得ARM至少一个授权许可。相比与截止于2005时仅有15亿ARM核被授权和销售,可以清楚地看到其加速增长。目前超过95%212的手机使用ARM技术,更令人印象深刻的是,该技术在超过25%的所有电子设备都存在。预计在2011年一年4就会有50亿个IP核被销售。特性和扩张如之前在历史部分提到的,许多在嵌入式系统中被广泛运用的标准选项被开发出来以提高ARM处理器在嵌入式系统开发领域潜在的应用和行业竞争。这些来自于各种各样的从例如包含浮点单元或多核这样的通用能力的特征集到例如拓展的Thumb指令集这样的更具体更高级选项的特征集。许多的特性并不被集成，直到最近修订的指令集。在更常见的特性去满足特殊目的的微处理器,他们中一些最著名的包括DSP和FPUs重复选项。在现代设计中多核也是一个常用的功能。通用单指令多数据(SIMD)13引擎多媒体应用在高端处理器也是一个可用的选项。SIMD通过操作系统现有的正在应用的端口进行透明的拓展。ARM开发更高级的版本指令集,名为NEON14,被开发作为ARMv7架构,使用更广泛的向量以及特殊的流水线。NEON大大优于老SIMD,至少两倍速度14。值得注意的最后一个选项是TrustZone15,多层基础设施,提供了软件和硬件的结合安全特性紧密集成到处理器。NEON、SIMD和TrustZone所有基础指令集的拓展。在接下来的会话,一个简单的图表将描述各种详细系列的处理器的特征。存在多个扩展补充基本的32位ARM 指令集:Thumb,Thumb-2和Jazelle16。Thumb是普通的ARM指令集减少到16位的一个子集。一个使用Thumb指令集的处理器仍然有32位宽寄存器和总线,它只是使用较小的指令。这是这么做,当使用16位内存,处理器执行一条指令不需要做两个获取,不然这显然将降低性能。这些指令在减压时减压。该系统的另一个优点是允许在必要时强调代码密度。现在,在最近的两个架构(ARMv6 & v7)Thumb-2也是可用的。实际上,Thumb-2皮层系列股票的特点。Thumb-2是一种混合与所有的拇指16位指令和指令集的一个子集原始手臂32位指令,指令长度设计无缝地使用变量。它拥有1718性能提升了25%在ARM和内存使用量减少26%。原来的32位ARM指令集仍然可以附带Thumb-2,事实上它甚至允许更多的无缝过渡。除了Thumb选项,Jazelle19是关注于一个ARM扩展Java支持。它既有硬件和软件组件。现在有两个版本的Jazelle:直接执行字节码(DBX)和运行时编译目标(RCT)。DBX的原作,允许Java字节码的直接执行。个随机对照试验,也称为ThumbEE使用准时制(JIT)和提前(AOT)编译方法。ThumbEE能够处理更大的各种各样的执行环境不仅仅是Java。由于这是更喜欢和支持实时和强制在v7应用程序驱动的处理器架构。在前面历史与营销的小节中,一些旧处理器系列名字(见表1)后面包含了几个字母。例如T、D、M、I 20,通常包含在一起,以及E和J。这些表明特定的特性。T的含义相当明显,表明之前提到的Thumb指令集的拓展。D和I都是独立的调试选项,前者站调试模式的联合测试行动小组(通过JTAG)的支持,而后者意义ICE支持是可用的。M是一个不那么简单,代表多级流水线和一个增强的乘法指令。这是相对于旧处理器。DSP功能拓展通过E表示,TDMI被包括。最后J表明Jazelle扩展。Cortex系列不再需要这些标签,因为许多这些特性被认为是产品的一部分,或被替换或更新。ARM开发的处理器之间的一个差异是使用的内存控制单元的类型。特定于应用程序的处理器也使用更先进的内存比嵌入式控制系统处理器的替代品。这些都是分别确定为内存管理单元(MMU)20和内存保护单元(微控制器)20。这些都是用于防止不必要的访问系统资源。MMU还包括硬件支持虚拟内存。处理器ARM初始的处理器按市场分为三类:经典处理器,嵌入式处理器和应用程序处理器。这些分类的添加功能的高级特性,以及提高性能和功能。这是证明了图如图1所示。除了这些,还有一些专业之外的处理器值得简要地承认存在主要三类SecurCore行等安全应用程序和目标处理器的FPGA。经典的处理器由之前的三个主要的ARM架构指令集版本组成。ARM7(实际上为ARM7TDMI或ARM7EJ)22,使用ARMv4指令集,随着ARM公司致力于推广Cotex系列替代相同等级的ARM7版本，目前ARM7基本已经完全过时。ARM9(ARMv5)23是仍在使用的低端单处理器DSP和java应用程序。ARM1124是基于ARMv6,仍然看到广泛使用作为一个潜在的选择在现代的发展。这几个老的处理器与Cortex 系列有一个二进制兼容允许设计升级,不需要大规模的软件设计。第二类的ARM处理器嵌入式处理器,命名为Cortex-R和Cortex-M，分别面向实时和微控制领域的应用。这类处理器运用ARMv7指令集,命名中包含cortex,因此包括Thumb-2指令集自动沿用Cortex系列标准。然而从应用程序方面去区分,这两种处理器系列都利用微处理器内存控制。他们还使用一个实时操作系统(RTOS)结合用户生成的代码。Cortex-R25使用更深流水线,并使用高时钟频率。它还利用紧耦合的内存(TCM)快速访问重要数据或指令需要直接访问。TCM被作为1级内存,它完全取代了缓存。相比之下,Cortex-M26与低功耗设计,代码密度和中断管理作为焦点。Cortex-M系列独家使用Thumb-2且没有ARM指令集。Thumb-2允许它保持8/16-bit竞争对手的低影响设计要求,同时保持提供32位机器的性能优势。最后一类ARM处理器的分类是应用程序处理器系列27，cortex A。这些都是用于高功能,被定义作为具有运行复杂的和完整的操作系统的能力。不同于嵌入式Cortex系列处理器,Cortex A应用程序处理器系列使用MMU代替微处理器中的内存控制单元。另外最多可选择为四核完全可以支持一致的一级缓存。Cortex A系列比其他系列处理器开放了更多的可用选项和拓展。某些特性作为选项的其他处理器家族自动包含在所有处理器,命名为Jazelle和NEON。不同系列处理器之前的不同特性在本章前面进行了详细的阐述，不同处理器系列的应用如表2所示。这幅图像的列是按照特定的组织架构来创建。上半部分使用颜色来显示处理器的分类,上面部分列出各自架构版本的处理器，下面部分列出的架构是这些处理器可用的各种选项特定的体系结构。附件2：外文原文BENCHMARKING ARM-BASED APPLICATION INTEGRATED SYSTEMS I. INTRODUCTIONThe line between a full processor and a microprocessor has always been a rather subjective one. Subsequently, there are only a few technologies straddle that line more so than Advanced RISC Machine (ARM) based applications processors 1. These behemoth microprocessors are at the heart of almost every major mobile handset 2 and capable of running full operating systems while still maintaining the low power advantages of their embedded brethren. As these applications processors become more adept, and subsequently the devices based on them become more feature laden, they become even more difficult to define. As the evolution of these devices progress, they will continue to become a category of their own, as such it stands to reason that they should be treated as a category of their own. The overwhelming majority of these application processors utilize the ARM Instruction Set Architecture (ISA) 2. ARM is used in a variety of different embedded systems ranging from the high-end applications processors to low end microcontrollers. This ISA is the Intellectual Property (IP) of the company ARM Holding Ltd. The company, founded on the development of an early version of the ARM ISA, has spent decades modernizing and expanding the architecture. This has led to many innovations that have contributed to the further differentiation between ARM and other embedded ISAs. Instead of manufacturing processors themselves, they license the IP cores to other companies allowing them to modify the technology to their own needs. This arrangement has resulted in literally hundreds 3 of companies producing billions of ARM processors per year 4 5. Rarely is licensing and manufacturing an exact copy of a core enough to meet the needs of a complex design. Thus licensees often times modify the core, package it with other components, or both. Using space reduction packaging technologies these companies are capable of containing an entire system to one footprint on a circuit board. While there are different methods to packaging system components together, for the purposes of this paper and project they shall all be referred to as integrated systems 6 7 8. These integrated systems come in many varieties of capability, function, and complexity. It should be obvious that many of these integrated system designers are direct competitors. It stands to reason then, that just like choosing any other option of processors it is important to be able to compare and differentiate between similarly purposed integrated systems. While a plethora of benchmarks exist for embedded systems and full processors, and even a few for applications processors, finding a benchmark that tests an entire system contained within a single device is much more difficult. Even when using the same core for the same design goal, two companies can and likely will have widely divergent components within the integrated system. Likewise, the methodology of packaging the components will have differences as well. It isnt enough just to test the core, but the entire system as a whole must be benchmarked due to the components being inseparable. After all, for this purpose, it behaves as a single device. OBJECTIVES Because of their prevalence, the intent of this thesis is to explore the topic of benchmarking integrated systems that are specifically in the applications market and powered by ARM technology. There are several questions on this subject that should be answered. Importantly, whether these ARM-based applications processors differ enough to be treated separately should be answered. The next question is whether or not full knowledge of the core obviates the necessity of testing the full system in these cases. Along with this, determination of whether or not there is an acceptable benchmark suite that is capable of adequately testing the full capabilities of an integrated system will be equally important. If there is not, then the reasons one hasnt been developed need to be investigated. The final consideration is what the future holds for these devices, and the part that will play. CONTRIBUTIONS This paper makes several contributions. The collection of technologies included within the boundaries of packaging technology that are dedicated to containing a system to a single footprint is shrouded in ambiguity and conflicting nomenclature. The terms system-on-chip, system-in-package, and package-on-package are frequently used in slightly different nuances, and occasionally interchangeably, while in other research instances they are heavily distinguished. This overview and explanation will help to remove this ambiguity and will clarify the all-encompassing definition of “integrated systems”. It is necessary to determine what the acceptable characteristics are for a standard benchmark intended for integrated systems. To do so, a brief summary of critical features that should be expected in a standard benchmark is overviewed. The topic of misusing benchmarks is also reviewed and discussed. The OMAP3530 9 integrated system will be tested with the benchmark suite MiBench 10. The results of running the benchmark are included, with thorough documentation, charts, time stamps, and other relevant information. A thorough exploration of the state of benchmarks applicable to the target platforms (ARM-based applications integrated system) shall be completed. This includes determining if the industry standards are sufficient as well as providing a succinct collection of previous relevant experiments and results. SUMMARY Competing designs of ARM-based applications integrated systems are widespread enough to warrant their own benchmarking standard. To test just the ARM cores is not sufficient to compare or contrast the capabilities of the integrated systems. Additionally application end processors balance the strengths of normal embedded microprocessors with full processors, thus benchmarking against one or the other category is inconclusive and superfluous. With the growing industry the necessity will continue to climb. Chapter 1 provides a detailed overview of the project and the thesis statement. The second chapter focuses on the background knowledge necessary for the project. This begins with a detailed overview of the ARM Instruction Set Architecture starting with its history and prominence in modern devices and ending with specific details of the architecture. The section on ARM is followed by a look at what makes an integrated system by overviewing the specifics of some of the packaging technologies that are used to contain an entire system to one footprint. Next a detailed look at the test device itself, the Beagle Board, is included. The background chapter is completed with an overview of benchmarking. Chapter 3 includes a close examination of preparing the Beagle Board for the experiment, a look at selecting the appropriate benchmark, and the specifics of the benchmark selected. Following this, the fourth chapter details the results of the work. This begins with an examination of the results of benchmarking the Beagle Board. The other prevalent part of this chapter looks at the results of researching various benchmarks for existing results and comparisons between system integrated circuits such as those between the OMAP and i.MX platforms. Chapter 5 concludes the thesis.II. BACKGROUNDIn order to understand the necessity of a benchmark suite specifically aimed at integrated systems that use ARM ISAs, it is imperative to have a background. As mentioned in the Introduction, ARM is very widely licensed and its use is rapidly expanding. These licensees are using ARM based technology in different ways to create their own systems. Some of these systems are integrated together on a single chip or within a package and sold as its own product; therefore, an overview is necessary of both ARM technology and packaging techniques for integrated systems. One such product is TIs OMAP series. The Beagle Board is a convenient interface with an OMAP processor, thus is used as a platform for benchmarking experiments. It is highly functional, and is adaptable to a large variety of projects. The Beagle Board also has the advantage of being fully open-source. This device will be further explored in the sections below. The study of benchmarks has been thoroughly explored, so it is not the purpose of this paper to broaden or expand this topic. However, it is necessary to examine some of what is available in order to highlight the absence of applicable benchmark suites. It will become clear that there are many benchmarks that do provide some suitable tests for these systems. However, none of these benchmarks are satisfactorily comprehensive. ARM One of the most common Instruction Set Architectures (ISA) being developed for modern applications is the Advanced RISC Machine (ARM). ARM is a 32-bit ISA based on the Reduced Instruction Set Computer (RISC) design strategy. This architecture has made sweeping advances since its conception, expanding into multiple embedded markets, particularly those related to consumer electronics. It is important to understand how widespread ARM cores have developed and how rapidly they have achieved that level of success in addition to the processor capabilities and architecture. History and Marketing Originally, ARM stood for Acorn RISC Machine and was developed by a branch of a small British company, named Acorn Computers Ltd, hoping to get into the business computing market. There were not any viable processor options that fit their needs or market goals, so they chose to develop a new architecture after being inspired by a RISC project completed by a group of Berkeley graduate students proving architecture development could be done on low budget and limited facilities. After completing the ARM1 primarily as a development project in 1985 11, eventually the ARM2 and later the ARM3 were marketed. In 1990, Apple Computer and Acorns silicon contractor, VLSI Technology, aided in researching the next stage in ARM development 5. These contributions lead the team to break off into its own company: Advanced RISC Machines Ltd. Eventually the company renamed itself ARM ltd (or ARM Holdings) in 1998 when it floated itself on the London stock market 5. ARMs first embeddable RISC core in 1991 was the result from the early joint efforts between Apple, Acorn and V-tech 11. This first embeddable core was also based off the new ARMv3 architecture, and was named the ARM6 as a result of a new core naming scheme. Over the next two decades several versions of the ISA were developed, the most recent being the ARMv7 debuting with the Cortex family in 2004 5. For a better visual of the architecture version as related to its processor family Table 1 has been included. This table has been simplified; there are a variety of sub-architecture versions that distinguish the differences between the families. Likewise some families exist over the span of several architectures, using different sub-architectures during the lifetime of that family. During this time ARM also developed a variety of innovations to allow more chip specializations and optio