EDA数字钟设计.doc

数 字 钟 - EDA课程设计姓 名： 专 业：班 级： 指导教师： 一、数字钟的设计要求（1）具有正确的时、分、秒计时功能。（2）计时结果要用6个数码管分别显示时、分、秒的十位和个位。（3）有校时功能。当键MINUTE按下时，分计数器以秒脉冲的速度递增，并按60min循环，即计数到59min后再回00。当HOUR键按下时，时计数器以秒脉冲的速度递增，并按24h循环，即计数到23h后再回00。二、数字钟顶层结构根据数字钟的功能要求，就可以对数字钟按照功能进行模块划分。图2-1是它的顶层电路原理图。在图2-1中，外界通过CLK端输入1Hz的脉冲信号。1Hz信号作为秒脉冲信号送入SECOND（60进制）计数器进行秒计时，满60s产生一个进位信号CARRY，经过或门被送入MINUTE（60进制）计数器进行分计数。当按下SECOND键后，1Hz秒脉冲信号通过或门被送入MINUTE（60进制）计数器进行分计数，从而实现快速校分功能。HOUR（24进制）计数器也是经过同样的过程实现计数和校时功能。时、分、秒计数器的输出均是十位和个位分开显示的8421BCD码，将这六组BCD码通过一个六选一数据选择器MUX6_1SCAN选出一组BCD码。由外界输入的CLKCAN信号作为MUX6_1SCAN的选择控制信号，然后再将选出的一组BCD码送至七段译码显示器进行译码。译码每输出结果同时送至6个LED数码管的a、b、c、d、e、f 7个段，至于哪个数码管能够显示，取决于扫描控制信号SEL的输出结果，即SEL选择哪个数码管，那个数码管就点亮。用多个（个）数码管显示数据时有并行显示和动态扫描显示两种方式。所谓并行显示，是个数码管同时被驱动，它需要同时对组BCD码数据进行编译，并输出6组LED段驱动信号去驱动个数码管的个显示段，共需要42个I/O管脚，另外还需要个BCD/段译码器。本设计采用动态扫描显示，每次仅仅点亮个数码管，各个数码管轮流被扫描点亮，如果扫描的速度足够快，由于人眼存在视觉暂留现象，就看不出闪烁。开始工作时，先从组数据中选出一组，通过段译码器译码后输出，然后选出下一组数据译码输出。数据选择的时序和顺序由个进制计数器SEL控制，与此同时，MUX6_1SCAN产生选通信号。这种显示方式需要的资源少，而且节能。图2-1 数字钟的顶层原理图三、数字钟各模块的VHDL源程序设计以下是数字钟各模块的VHDL程序及部分主要模块的仿真波形。整体模块VHDL代码:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY s_clock_signal IS PORT(clk,reset:IN STD_LOGIC;ca1,ca2,ca3:out std_logic; seline : out std_logic_vector(2 downto 0); seg7 : out std_logic_vector(7 downto 0); seg_s_l,seg_s_h,seg_m_l,seg_m_h,seg_h_l,seg_h_h:buffer integer range 0 to 9);END ENTITY s_clock_signal;ARCHITECTURE mzm OF s_clock_signal IS SIGNAL sec1_t,sec2_t, min1_t,min2_t,hour1_t,hour2_t:integer range 0 to 9; SIGNAL carry1,carry2,carry3: STD_LOGIC; SIGNAL cnt : std_logic_vector(2 downto 0); SIGNAL cnt_freq : integer range 0 to 999; SIGNAL sel : std_logic_vector(2 downto 0); SIGNAL clk_1Hz:std_logic; function i2seg7(i : in integer range 0 to 9)return std_logic_vector isvariable seg7 : std_logic_vector(7 downto 0);begincase i iswhen 0 =seg7 := x3f;-digital tubes display 0 to 9when 1 =seg7 := x06;when 2 =seg7 := x5B;when 3 =seg7 := x4F;when 4 =seg7 := x66;when 5 =seg7 := x6D;when 6 =seg7 := x7D;when 7 =seg7 := x07;when 8 =seg7 := x7F;when 9 =seg7 := x6F;when others =seg7 := (others = 0);end case;return seg7;end function i2seg7;BEGIN p1:PROCESS(clk_1Hz,reset,sec1_t,sec2_t) BEGIN IF reset=1 THEN sec1_t=0; sec2_t=0; ELSIF rising_edge(clk_1Hz) THEN IF sec1_t=9 THEN sec1_t=0; IF sec2_t=5 THEN sec2_t=0; ELSE sec2_t=sec2_t+1; END IF; ELSE sec1_t=sec1_t+1; END IF; IF (sec1_t=9 AND sec2_t=5) THEN carry1=1; ELSE carry1=0; END IF; END IF; seg_s_l=sec1_t; seg_s_h=sec2_t; END PROCESS p1; p2:PROCESS(reset,min1_t,min2_t,carry1) BEGIN IF reset=1 THEN min1_t=0; min2_t=0; ELSIF rising_edge(carry1) THEN IF min1_t=9 THEN min1_t=0; IF min2_t=5 THEN min2_t=0; ELSE min2_t=min2_t+1; END IF; ELSE min1_t=min1_t+1; END IF; IF (min1_t=9 AND min2_t=5) THEN carry2=1; ELSE carry2=0; END IF; END IF; seg_m_l=min1_t; seg_m_h=min2_t; END PROCESS p2; p3:PROCESS(reset,hour1_t,hour2_t,carry2,carry3) BEGIN IF reset=1 THEN hour1_t=0; hour2_t=0; ELSIF rising_edge(carry2) THEN IF (hour1_t=3 AND hour2_t=2) THEN hour1_t=0; hour2_t=0; ELSE IF hour1_t=9 THEN hour1_t=0; IF hour2_t=2 THEN hour2_t=0; ELSE hour2_t=hour2_t+1; END IF; ELSE hour1_t=hour1_t+1; END IF; END IF; IF (hour1_t=0 AND hour2_t=0) THEN carry3=1; ELSE carry3=0; END IF; END IF; seg_h_l=hour1_t; seg_h_h=hour2_t; END PROCESS p3;ca1=carry1;ca2=carry2;ca3=carry3;p4:process(clk, reset,sel) beginif reset = 1 thencnt 0);cnt_freq = 0;clk_1Hz = 0;elsif rising_edge(clk) thenif cnt = 7 then -6 counter to scan digital tubescnt 0);elsecnt = cnt + 1;end if;if cnt_freq = 999 then-1k dividcnt_freq = 0;clk_1Hz = not clk_1Hz;elsecnt_freq = cnt_freq + 1;if cnt_freq = 499 thenclk_1Hz sel = 000;seg7 sel = 001;seg7 sel = 010;seg7 sel = 011;seg7 sel = 100;seg7 sel = 101;seg7 sel = 110;seg7 sel = 111;seg7 sel = ZZZ;end case;seline=sel+001;end if;end process p4;END mzm;（1）秒计数器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY second IS PORT(clk,reset:IN STD_LOGIC; sec1,sec2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); carry:OUT STD_LOGIC);END second;ARCHITECTURE rt1 OF second IS SIGNAL sec1_t,sec2_t:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk,reset) BEGIN IF reset=1 THEN sec1_t=0000; sec2_t=0000; ELSIF clkevent AND clk=1 THEN IF sec1_t=1001 THEN sec1_t=0000; IF sec2_t=0101 THEN sec2_t=0000; ELSE sec2_t=sec2_t+1; END IF;图3-1 秒计数器 ELSE sec1_t=sec1_t+1; END IF; IF sec1_t=1001 AND sec2_t=0101 THEN carry=1; ELSE carry=0; END IF; END IF; sec1=sec1_t; sec2=sec2_t; END PROCESS;END rt1;图3-2 秒计数器仿真波形图3-3 秒计数器局部放大仿真波形（2）分计数器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY minute IS PORT(clk,reset:IN STD_LOGIC; min1,min2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); carry:OUT STD_LOGIC); END minute;ARCHITECTURE rt1 OF minute IS SIGNAL min1_t,min2_t:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk,reset) BEGIN IF reset=1 THEN min1_t=0000; min2_t=0000; ELSIF clkevent AND clk=1 THEN IF min1_t=1001 THEN min1_t=0000; IF min2_t=0101 THEN min2_t=0000; ELSE min2_t=min2_t+1; END IF; ELSE min1_t=min1_t+1; END IF;图3-3 分计数器 IF min1_t=1001 AND min2_t=0101 THEN carry=1; ELSE carry=0; END IF; END IF; min1=min1_t; min2=min2_t; END PROCESS;END rt1;图3-4 分计数器仿真波形图3-5 分计数器局部放大仿真波形（3）时计数器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY hour IS PORT(clk,reset:IN STD_LOGIC; hour1,hour2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); carry:OUT STD_LOGIC);END hour;ARCHITECTURE rt1 OF hour IS SIGNAL hour1_t:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL hour2_t:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk,reset) BEGIN IF reset=1 THEN hour1_t=0000; hour2_t=0000; ELSIF clkevent AND clk=1 THEN IF hour1_t=0011 AND hour2_t=0010 THEN hour1_t=0000; hour2_t=0000; ELSE IF hour1_t=1001 THEN hour1_t=0000; IF hour2_t=0010 THEN hour2_t=0000; ELSE hour2_t=hour2_t+1; END IF; ELSE hour1_t=hour1_t+1; END IF; END IF; IF hour1_t=0000 AND hour2_t=0000 THEN图3-6 时计数器 carry=1; ELSE carry=0; END IF; END IF; hour1=hour1_t; hour2seg7 := 10111111;when 1 =seg7 := 10000110;when 2 =seg7 := 11011011;when 3 =seg7 := 11001111;when 4 =seg7 := 11100110;when 5 =seg7 := 11101101;when 6 =seg7 := 11111101;when 7 =seg7 := 10000111;when 8 =seg7 := 11111111;when 9 =seg7 := 11100111;when others =seg7 := (others = 0);end case;return seg7;end function i2seg7;component s_clock_signal isport(rst : in std_logic;- reset time to 00:00:00clk : in std_logic;- assume 1 Hzseg_s_l : out integer range 0 to 9;seg_s_h : out integer range 0 to 9;seg_m_l : out integer range 0 to 9;seg_m_h : out integer range 0 to 9;seg_h_l : out integer range 0 to 9;seg_h_h : out integer range 0 to 9);end component s_clock_signal;beginu1: s_clock_signal port map(rst = rst,clk = clk_1Hz,seg_s_l = seg_s_l,seg_s_h = seg_s_h,seg_m_l = seg_m_l,seg_m_h = seg_m_h,seg_h_l = seg_h_l,seg_h_h = seg_h_h);process(clk, rst) isbeginif rst = 0 thencnt 0);cnt_freq = 0;clk_1Hz = 0;elsif rising_edge(clk) thenif cnt = 5 thencnt 0);elsecnt = cnt + 1;end