Verilog比较好的一篇教程.ppt

,Verilog,MattTsai,VerilogApplicationIntroductiontoCadenceSimulatorsSampleDesignLexicalConventionsinVerilogVerilogDataTypeandLogicSystemStructuralModelingModelingDelayUsingCompilerControlsVerilogOperatorsBehavioralModelingSupportforVerificationIntroductiontoUsingaVerilogTestBenchModelingMemoriesHighLevelConstructsinVerilogUserDefinedPrimitivesAnnotatingSDFTiming,IEEE1364-1995,IEEE1364-2001Behavioral:無法看出電路特性RTL:可以看出電路特性(logicsynthesis)Structural:bulit-inprimitives,UDPsRTLandstructural可混合描述Behavioral和RTL的區分要靠經驗,Behavioralfor(;)for(;).,RTLalways(sloraorb)if(!sl)out=a;elseout=b;,Compilation(1)Initialization(2)Simulation(3)Verilog-XLsimulator:Interpretive不會有暫存檔(1)(2)(3)一次完成NCVerilogsimulator:compiledsimulationncviog(1)ncelab(2)ncsim(3)當project很大時,只針對要修改部分重新compile即可VHDLandVerilog可以作整合SimulationalgorithmsTime-based(SPICE)Event-based(Verilog-XLandNCVerilog)Cycle-based(依照clock,更大的time-based),3-9,3-3,verilogmux.vtestbench.vverilogfrun.fThewaveformdisplaytool-signalscanReaddatafromdatabaseSHMdatabase(非IEEEstandard,onlyCadence)VCD(ValueChangeDump)database(IEEEstandard),initialbegin$shm_open(“lab.shm”);$shm_probe(“AS”);end,initialbegin$dumpfile(“lab.dump”);$dumpvars();end,3-17,4-26,3-27,Testbench-behavioralProceduralblockInitialalways,Templatemoduletestbench/Datatypedeclaration/Instantiatemodules/Applystimulus/Displayresultsendmodule,moduletestbench/Datatypedeclarationrega,b,sel;wireout;/InstantiatemodulesMUX2_1mux(out,a,b,sel);/Applystimulusinitialbegina=0;b=0;sel=0;#5b=0;#5b=1;sel=1;#5a=1;$finish;end/Displayresultsinitial$monitor($time,”out=%ba=%bsel=%b”,out,a,b,sel);endmodule,4-15,Waveformdatabase(SHMandVCD),$shm_open(“lab.shm”);$shm_probe();$shm_close;$shm_save;,$dumpfile(lab.dump”);$dumpvars();$dumpflush;$dumpoff;$dumppon;$dumplinit();$dumpall;,includeglobal.vverilogmux.vglobal.vtimescale1ns/100psLumpeddelaynorn1(net1,a,b);or#3o1(out,c,net1);Distributeddelaynor#2n1(net1,a,b);or#1o1(out,c,net1);ModulepathdelaySpecify(A=O)=2;(A=O)=3;(A=O)=1;/statedependentpathdelayif(a)(b=x)=(5:6:7);/statedependentdelay無else的語法Endspecifyspecifyblock,InsidecodeCommandline,8-3,8-16,Selectingsimulationdelaymode,Commandline+delay_mode_unit+delay_mode_zero+delay_mode_path+delay_mode_distributed,Insidecodedelay_mode_unitdelay_mode_zerodelay_mode_pathdelay_mode_distributed,Unitandzerodelaymodes:ignoresallspecifyblocks,andreducesgatetounitorzerovalue.Distributedmode:ignoresspecifyblocks,butleavesgatedelaysalonePathmode:ignoresgatedelays,butleavesspecifyblocksalone,Parallelconnection(a,b=q,qb)=15;(a=q)=15;(b=qb)=15;Fullconnection(a,b*q,qb)=15;(a=q)=15;(b=q)=15;(a=qb)=15;(b=qb)=15;,TimingchecksinVerilog(物理特性)Setup,hold,pulsewidth,clockperiod,skew,recoverySDF(StandardDelayFormat)tool-independenttextformatforrepresentingtimingdataAllowstimingdatatobesharedbetweentoolsInterconnectdelay因製程技,使interconnectiondelay比gatedelay大,下晶片需SDFFileIOPATHdelayAdelayonlegalpathfromaninputporttoanoutputportofadevice,8-38,21-5,8-30,UsingCompilerControls,Vendor-suppliedveriloglibrariesSimulatingwithveriloglibrariesEncryptingyourverilogsourcecodeAdditionalsimulator-specifictopics,Modelingcomponentlibraries,TocreateverilogmodellibrariesModeleachcomponent(orcell)asseparatemodulePlacerelatedmodulesineitheronefileoronedirectoryYoucanmodelthefunctionalityofeachcellattwolevelsStructuralUDPs,combinationallogicandsimplesequentiallogicBehavioralProceduralblockRAM,ROM,9-5,verilogtest.vvlib.v若無-v會全部compile有-v用到才compile也可無celldefine及-v,如一般的file,verilogtest.vy./mylib+libext+and2.v檔案名稱要和module名字相同一個file內只能有一個module這些files全部都要放在librarydirectory,(Verilogmodellibrarydirectory),Theuselibcompilerdirective(onlyCadence),moduleadder(c_out,sum,a,b,c_in);Outputc_out,sum;Inputa,b,c_in;uselibdir=/libs/FAST_LIB/SN7486u1(half_sum,a,b);Uselibdir=/libs/TTL/libext=.vfile=/libs/TTL/udp.libSN7408u2(half_c,a,b);SN7486u2(sumc,c_in,half_sum);SN7432u2(c_out,tmp,half_c);SN7486u1(half_sum,a,b);/ERRORendmodule,9-18,SizingandsigninginVerilog,等號右邊一定是對的,指定到左邊時會自動truncate,modulesign_size;reg3:0a,b;reg15:0c;reg3:0regb,rega,num;initialbegina=-1;/1111b=8;c=8;#10b=b+a;/10111-0111endinitial#30num=regb%rega;/num的正負號和regb相同endmodule,10-5,Equalityoperator=:assignmentoperator=:theequalityoperator(數值比對)1=1=:theidentityoperator(型態上)x=xval=rega=regb;/rega=1,regb=1,val=1val=rega=regc;/rega=1,regb=x,val=xval=rega=regc;/rega=z,regb=z,val=xval=rega=regb;/rega=x,regb=x,val=1Conditionaloperatorassignout=sel=2b00?a:sel=2b01?b:sel=2b10?c:d;,10-21,10-28,Concatenationnew=regc4:3,regd7:5,regb2;Replicationnew=4regb,2regc;ProceduralblockBehavioralmodeling,notstructuralmodelingTwotype:initial,alwaysIthasthefollowingcomponentProceduralassignmentstatementsHigh-levelconstructs(loops,conditionalstatements)TimingcontrolsProceduralassignmentInsideproceduralblocks等號左邊要reg才行,Proceduraltimingcontrol#,wait所有的proceduralblocks同時執行,alwayswait(set)begin(posedgeclk)#3q=1;#10q=0;wait(!set);end,1.有可能會有racecondition,但並非每次都會有racecondition2.racecondition是simulation才會有,可以改變set信號再去Simulation就可以了3.實際電路不會,因本身就有delay了,11-39,Inter-assignmenttemp=b;(posedgeclk)a=temp;Intra-assignmenta=(posedgeclk)b;,posedgeclk右邊算出左右,右邊算出,暫存在bposedgeclk左右,Data,c,b,clk,IntercIntrab,Conditionalstatementsif-elsecaseIf-else階層超過2層時會有判斷優先權順序的路出現,故改用case若無else敘述,電路會變得很大Continuousassignment(assign)Proceduralblock中不可用assignwireout;assignout=a/implicit,Verificationsystemfunctionsandtasks$time(64-bits)$stime(32-bits)$realtime(realnumber)$display$strobe$write$monitorPrintingformattedtimeinformation$timeformat(,)$timeformat(-9,2,”ns,10);$display(“%t”,$realtime);,Toreadthecurrentsimulationtime,Tosupporttextoutput,$writevs.$display:$display會自動換行$strobe一定在event-query的最後面,initialbegin#10date=20;$strobe($time,data);/30$display($time,data);/20data=30;end,initialbeginintegerMCD1;/每個檔只有一個bit為1,有一個bit保留,故最多可以開31個檔MCD1=$fopen(“lab.dat”);$fdisplay(MCD1,”systemresetattime%d”,$time);$fwrite(MCD1,”systemresetattime%d”,$time);$fstrobe(MCD1,”systemresetattime%d”,$time);$fmonitor(MCD1,”systemresetattime%d”,$time);$fclose(MCD1)end,Fileoutput,14-20,Fileinput$readmemb$readmemh,reg0:7mema0:1023;readmemb(“mem_file.txt,mema);,0000_00000110_00010011_0010/addresses3-255arenotdefined100/hex1111_11003FF1110_0010,mem_file.txt,0000000001100001001100101111110011100010,0,256,1023,14-26,Designorganization,Includefiles,Designfiles,Fileinput:Simulus,Expectpatterns,Vendorlibraries,Fileoutput:Stimulus,resultpatterns,simulator,simulation,compilation,Includefiles,moduleclk_gen(clk);outputclk;regclk;include“common.txt”.endmodule,/common.txtparameterinitial_clock=1;parameterperiod=1;parametermax_cyc=1;parametersim_end=period*max_cyc;,1.parameter獨立在某一檔案中,並且詳細說明2.改變parameter,重新compile即是新的design,Testbench給pattern的方式,InlineLoop(behavioral),pattern要有規則array,/inlineinitialforkdata_bus=8h00;addr=8h3f;#10data_bus=8h45;#30addr=8h45;#60$finish;join,/loopinitialbeginfor(;)(negedgeclk)stimulus=1;#20$finish;end,/arrayinitialbegin#20stimulus=stim_array0;#20stimulus=stim_array1;#20stimulus=stim_array2;end,Verilogtaskandfunction,Task:input,output,inout,timingFuinction:input,returnvalue,combinational,可建立自己的operatorFunction一定在等號右邊,不一定要在proceduralblcok中Task:只能出現在proceduralblock中,always#5clk=!clk;taskngg_clocksinput31;0number_of_edges;repeat(number_of_edges)(negedgeclk);endtaskinitialbeginneg_clocks(3);end,modulefoo;input7:0loo;output7:0goo;wire7:0goo=test(loo);function7:0testinput7;0bus;test=return_test;endfunctionendmodule,17-7,不可synthesize,=uselibinitialmemory/WaitString(5-17)Namedevent(11-17),所有的module不一定有I/OPort名稱大小寫有差!但compiler會視為相同東西宣告int