(内存基本知识)_DRAM工作原理.ppt

DRAM工作原理DRAM工作原理,DynamicRandomAccessMemoryEachcellisacapacitor+atransistorVerysmallsizeSRAMusessixtransistorspercellDividedintobanks,rows&columnsEachbankcanbeindependentlycontrolled,DRAM,MainMemoryEverythingthathappensinthecomputerisresidentinmainmemoryCapacity:around100Mbyteto100GbyteRandomaccessTypicalaccesstimeis10-100nanosecondsWhyDRAMforMainMemory?Costeffective(smallchipareathanSRAM)HighSpeed(thanHDD,flash)HighDensity(Gbyte)MassProduction,Mainmemory,Notation:K,M,GInstandardscientificnomenclature,themetricmodifiersK,M,andGtorefertofactorsof1,000,1,000,000and1,000,000,000respectively.ComputerengineershaveadoptedKasthesymbolforafactorof1,024(210)K:1,024(210)M:1,048,576(220)G:1,073,741,824(230)DRAMdensity256M-bit512M-bit,DRAMDensity,WhatisaDRAM?DRAMstandsforDynamicRandomAccessMemory.RandomaccessreferstotheabilitytoaccessanyoftheinformationwithintheDRAMinrandomorder.Dynamicreferstotemporaryortransientdatastorage.Datastoredindynamicmemoriesnaturallydecaysovertime.Therefore,DRAMneedperiodicrefreshoperationtopreventdataloss.,Memory:DRAMpositionSemiconductormemorydeviceROM:NonvolatileMaskROMEPROMEEPROMFlashNAND:lowspeed,highdensityNOR:highspeed,lowdensityRAM:VolatileDRAM:DynamicRandomAccessMemorySRAM:StaticRandomAccessMemoryPseudoSRAM,DRAMTrend:FutureHighSpeed-DDR(333MHz500MHz),DDR2(533800Mbps),DDR3(8001600Mbps)-Skew-delayminimizedcircuit/logic:post-chargelogic,wave-pipelining-NewArchitecture:multi-bankstructure,highspeedInterfaceLowPower-5.5V=3.3V(sdr)=2.5V(ddr)=1.8V(ddr2)=1.5v(ddr3)=1.2v?-SmallvoltageswingI/Ointerface:LVTTLtoSSTL,opendrain-LowPowerDRAM(PASR,TCSR,DPD)HighDensity-Memorydensity:32MB=64MB=.1GB=2GB=4GB-applicationexpansion:mobile,memoryDBforshock(thanHDD)-Processshrink:145nm(03)=120nm(04)=100nm=90nm=80nmOtherTrends-CostEffectiveness,TechnicalCompatibility,Stability,Environment.Reliability,StaticRAM,SRAMBasicstorageelementisa4or6transistorcircuitwhichwillholda1or0aslongasthesystemcontinuestoreceivepowerNoneedforaperiodicrefreshingsignaloraclockUsedinsystemcacheFastestmemory,butexpensive,DynamicRAM,DRAMDensertypeofmemoryMadeupofone-transistor(1-T)memorycellwhichconsistsofasingleaccesstransistorandacapacitorCheaperthanSRAMUsedinmainmemoryMorecomplicatedaddressingscheme,RefreshinDRAMs,Capacitorleaksovertime,theDRAMmustbe“REFRESHED”.,CapacitanceLeakage,SRAMvs.DRAM,DRAMLeadFrameandWirebonding,DRAMArchitecture,SDRAMhasthemultibankarchitecture.ConventionalDRAMwasproductthathavesinglebankarchitecture.Thebankisindependentactive.memoryarrayhaveindependentinternaldatabusthathavesamewidthasexternaldatabus.Everybankcanbeactivatingwithinterleavingmanner.Anotherbankcanbeactivatedwhile1stbankbeingaccessed.(Burstreadorwrite),MultiBankArchitecture,DRAMMultiBankArchitecture,DRAMSingleBankArchitecture,DRAMBlockDiagram(1),DRAMBlockDiagram(2),DRAMCoreArchitecture,DRAMAddress,DRAMCoreArchitecture,16bitDRAMCore,DRAMDataPath,DRAM1T-1Cstructure,RAS:rowaddressstrobeCAS:columnaddressstrobeWE:writeenableAddress:codetoselectmemorycelllocationDQ(I/O):bidirectionalchanneltotransferandreceivedataDRAMcell:storageelementtostorebinarydatabitRefresh:theactiontokeepdatafromleakageActive:sensedatafromDRAMcellPrecharge:standbystate,DRAMKeyword,DRAMcellarrayconsistofsomanycells.Onetransistor&OnecapacitorSmallsenseamplifierLowinputgainfromchargesharingCS:Smallstoragecapacitor:25fFCBL:Largeparasiticcapacitor:over100fFVc:StoragevoltageVCP:halfVcforplatebiasVBLP:halfVcforBLprechargebias(initialbias),DRAMCell,DRAMArrayOverview,SimplifiedExample,ActivatingaRow,ActivatingaRowMustbedonebeforeareadorwriteJustlatchtherowaddressandturnonasinglewordline,Writing,WritingArowmustbeactiveSelectthecolumnaddressDrivethedatathroughthecolumnmuxStoresthechargeonasinglecapacitor,2019/12/13,33,可编辑,Reading,ReadingArowmustbeactiveSelectthecolumnaddressThevalueinthesense-amplifierisdrivenbackout,TheSense-Amplifier,Sense-AmplifierApairofcross-coupledinvertersBasicallyanSRAMelementWeakerthanthecolumnmuxWritedatawill“outmuscle”thesense-amplifierKeepsthedataatfulllevel,Precharge,PrechargeInactivestate(nowordlinesactive)PrechargecontrollinehighTiesthetwosidesofthesense-amptogetherThismakesthebitlinesstayatVDD/2Onlystableaslongastheprechargecontrollineishighotherwisethisisunstable!Nocapacitorsconnected,ActivationRevisited,ActivationTurnofftheprechargecontrollineMakesthesense-ampunstableitwantstogotoeither0or1insteadofstayingatVDD/2Averyveryveryshorttimelater,turnonthewordlineoftherowtobeactivated.CouplesthecapacitorontothebitlinesThis“tips”thebitlinestoholdthestoredvalue.Thesense-ampamplifiesthecapacitorbacktofullvalue.(hencethename!),DRAMRefresh,Becausethestoredmemoryvalueisstoredonacapacitor(thathasresistiveleakage),thememoryisconstantly“forgetting”itscontents.Eventually,thechargeonthecapacitorwontbeenoughtotipthesense-ampintherightdirection.But,activatingarowrestoresthecellsonthatrowtotheirfullvalue.Thereisanexplicitrefreshcommandthatjustactivatesandimmediatelydeactivatesarow.TheDRAMhasaninternalcounterthatcontainsthenextrowtoberefreshedandincrementseverytimearefreshcommandisissued.,DRAMRefresh,DataRetentionTimeDRAMCellconsistsofcapacitancewhichhasleakageastimeRetentiontimeisperiodformaintainingitsdataespecially1dataUsually,DRAMCellrefreshperiodis64msRefreshTimingtREF:Realcellretentiontime(Devicecharacteristic),ex)90ms(Hot)tRFC:Refreshcommandoperatingtime,ex)75nsRefreshSpec.BurstRefresh:64msDistributerefresh-128Mbdevice(12Rowaddress):64ms/4K=15.6us-256Mbdevice(13Rowaddress):64ms/8K=7.8us,AUTORefresh,WhenthiscommandisinputfromtheIDLEstate,thesynchronousDRAMstartsautorefreshoperation.Duringtheauto-refreshoperation,refreshaddressandbankselectaddressaregeneratedinsidetheSynchronousDRAM.Foreveryauto-refreshcycle,theinternaladdresscounterisupdated.Accordingly,8192timesarerequiredtorefreshtheentirememory.Beforeexecutingtheauto-refreshcommand,allthebankmustbeIDLEstate.Inaddition,sincethePrechargeforallbankisautomaticallyperformedafterauto-refresh,noPrechargecommandisrequiredafterauto-refresh.,SelfRefresh,Self-RefreshEntrySELF:WhenthiscommandisinputduringtheIDLEstate,theSynchronousDRAMstartsself-refreshoperation.Aftertheexecutionofthiscommand,selfrefreshcontinueswhileCKEisLow.Sinceself-refreshisperformedinternallyandautomatically,externalrefreshoperationsareunnecessary.Self-RefreshExitSELFX:Whenthiscommandisexecutedduringself-refreshmode,theSyncDRAMcanexitfromself-refreshmode.Afterexitingfromself-refreshmode,theSyncDRAMenterstheIDLEstate.,noPrechargecommandisrequiredafterauto-refresh.,ModeRegister,SpecialcommandtoinitializetheDRAMBurstlengthInterleavingCASLatency(readcommandtoreaddatainclocks)ForDDR,DLLresetisalsohere,MRSBlockDiagram,ModeRegister,Becausethestoredmemoryvalueisstoredona,ExtendedModeRegister,SpecialcommandtoinitializeDDRDRAMDDRonlydontuseforSDRDLLEnableDriveStrength,DRAMInterface,CommandSignalsCAS#,RAS#,WE#,CS#CS#+CAS#=ReadCS#+WE#+CAS#=WriteCS#+RAS#+CAS#=RefreshCS#+RAS#=ActivateCS#+WE#=BurstStopCS#+WE#+RAS#=PrechargeCS#+WE#+CAS#+RAS#=MRSorEMRSAllothers:NOPOthersignals:CLK,DATA,DQS,DRAMInterface,AllsignalsgofromthehosttothememoryexceptDQSanddatawhicharebi-directional.,ReadCycle,TypicalReadCycleBurstLength4CASLatency=3,WriteCycle,TypicalWriteCycleBurstLength4Writelatencyisalwayszero,DataClocking,CLKisalwaysdrivenbythehostDQSisdrivenbywhoeverisdrivingthedataNVchipdrivesonwritecyclesMemorychipdrivesonreadcyclesThisschemeiscalled“source-synchronousclocking”EliminatesalotofthetimingheadachesfromSDRAddsmargin,Latencies,AllkindsActivatetoPrechargeLastwritedatatoprechargeActivatetoReadActivatetoWriteRefreshcycletimeRefreshintervalMinimumrowactivetimeYadd