Basic High-Speed Transceiver Architecture.ppt

BasicHigh SpeedTransceiverArchitecture DenisLu APRSC 2 Agenda IntroductionStratixIVGXTransmitterPathReceiverPath Introduction 4 WhatisaTransceiver Combinationtransmitter receiverusedwhensendinghigh speeddigitaldata controlssignalsacrossphysicalmediumBoardtracesOpticalfiberCAT5cableUsedinthePHY physical layer 5 Definitions PhysicalCodingSub Layer PCS DigitallogicthatpreparesparalleldatafortransmissionacrossaphysicalmediumorrestoresdatatooriginalformEx Encoding decoding scrambling descramblingPhysicalMediaAttachment PMA ConvertsdigitaldatatoserialanalogstreamorreverseConnectstophysicalmediumEx Paralleltoserialconversion StratixIVGX 7 StratixIVGXChipLevel Transceiverblock withfour8 5Gbpstransceivers andtwo3 2Gbpstransceivers PCIExpresshardIPblocks High speedLVDSI ObankswithDPAcapability 8 8 Bluetext EnhancementstoStratixIIGXFPGA TransceiverFeatureSet 9 TransceiverBlock 1 TheCMUcanbeconfiguredasatransceiverchannelwithPMAonly 10 4Channels 2CMUConfiguration 11 6ChannelsConfiguration 12 6ChannelsConfiguration PMAOnly 13 13 ProtocolSupportSummary Bluetext EnhancementstoStratixIIGXFPGA 14 14 FeatureComparison Transceivers 15 15 TransceiverDataRates PCS PMAChannels WewillbinfortransceiverspeedinStratix IVGXFPGAs 16 16 TransceiverDataRates PMAOnlyChannels TransmitterindependentofreceiverChannelavailablewhennotusedasaclockmultiplierunit CMU PMAonlychannelscouldpotentiallyrunfasterUsesthesamePMAblockasPMA PCSchannelswhichrunat8 5GbpsSpeedlimitedbycoretotransceiverinterfacetimingbecausethechanneldoesnothaveaPCStobufferdataTopspeedwillbereassessedaftercharacterization stretchgoalistoachieve6 375GbpswithPMAonlychannels 17 StratixIVGXTransceiverBlockTopology F H K N oneside bothsides 8 8 0 16 16 0 24 16 8 36 24 12 48 32 16 D Total 8G 3G 18 DynamicReconfigurationofChannels withoutreconfiguringtheFPGAcoreChangePMAsettingsOutputdifferentialvoltageVodTransmitterpre emphasisReceiverequalizationSwitchdatarateexamples1G 2G and4GFibreChannel155 Mbps 622 Mbps and2 448 GbpsSONET SDH OC 3 STM 1 OC 12 STM 4 andOC 48 STM 16 ChangePCSandclockdomainsettingsSwitchbetweenSONET SDH GbEandFibreChannel 19 AdaptiveEqualization AlteradevelopedAdaptiveDispersionCompensationEngine ADCE AutomaticallymonitorsandadjuststhereceiveequalizerforthebesteyeopeningPVTcontinuouslymonitoredandcompensatedBlindequalizationrequiresnotrainingpatternRequiresDCbalancedencodingschemewithampletransitionsToseePlug PlaySignalIntegrityinaction watchthedemoat StratixIVGXVSVirtex5 21 FastestTransceiverDataRate TheXCVRdataratesofthelargestVirtex 5FXTdeviceislimitedto5 0Gbpscommercial 4 25GbpsIndustrial Provisionsforcustomerstouseafastspeedgradedeviceoverindustrialtempwherethecoreoperatesatmidspeedgradebutthetransceiveroperatesatfastspeedgrade 6 375Gbps ThecustomermustobtainapasswordforQuartusIItorunthisconfiguration 22 40 nmTestChipEyeDiagram 8 5Gbps Seriallinkrate 3G 6G 8G Technologynode 0 13 0 09 0 065 0 040 40 nmtechnologyfacilitatessufficientmarginforproductionsolutionof8 5Gbps XCVRs Guardband Requiredmargintoguaranteerobustmulti channelperformanceacrossPVT Targetperformance Maximumdataratetargeted Superiorperformance Performanceachievedinexcessofcommonindustryspecifications 10G TJ 27 5psRJ 1 23psrmsDJ 10 3ps 23 ProtocolStandardSupportComparison 24 PCIExpress NotallPCIExpressstandardsareequalXilinxdoesnothaveasolutionforx8PCIeGen2StratixIVGXistheonlyFPGAtoofferPCIExpress2 0hardIP upto4 TheVirtex 5LXTcanonlysupport1HIPblock TheVirtex 5FXTsupportsamaxof2HIPblocks 25 TransceiverFeatureComparison CH3 StratixIVGXPMA CMU1 CH2 CMU0 CH1 CH0 ADCE ADCE ADCE ADCE Enhancedversiontoreducepower Enhanced lowerjitter TransmitterPath 27 TransmitterPath Convertsparalleldatapatterntohigh speedserialdatastreamEmbedsclockintosingleserialdatastreamsodatacanberestoredatreceiverFunctionallysimpler fewerblockswhencomparedtoreceiver 28 TransmitterPath TransmitterBlockDiagramTransmitterPCSTransmitterPMA 29 TransmitterBlockDiagram FromFPGA PhaseCompFIFO CentralBlock PowerDown Reset CMU ByteSerializer 8B 10BEncoder BitSerializer PCS PMA 30 TransceiverPCSBlocks PhasecompensationFIFOByteserializer8B 10Bencoder 31 TransmitterPhaseCompensationFIFO ShallowFIFOthatcompensatesforphasedifferencesbetweenFPGAcoreandtransceiverPCS TXPhaseCompFIFO RD CLK WR CLK Transceiver PLD LowSpeedclockfromtransmitterPLL tx clkoutorcoreclkout PIPE tx coreclk 32 ByteSerializer ByteserializerreducesPLDclockratewhilemaintainingthedesiredlinerateUsedwhentransmitteddatarateistoofastforthecorelogic250MHzmaximumclockPLDlimitationDoublescoredatawidth32 bitor40 bitinputindoublewidthmode16 bitor20 bitinputinsinglewidthmodeLeastsignificantbytetransmittedfirst 33 ByteSerializer ByteSerializerbypassed ByteSerializerEnabled DataFlow 34 8B 10BEncoder Converts8 bitdata 1 bitcontrolto10 bitcodegroupsEnsuresenoughtransitionsontransmitteddatatomaintainsynchronizationwithreceiverAvailableinsingleanddoublewidthmodeDoublewidthmodeoperatesinaparallellinkedmodewithtwo8B 10BencodersCanbebypassedEx Designusedscrambling 35 TransmitterPMABlocks TransmitterbufferTransmitterClockManagmentUnit CMU Serializer 36 Serializer TwomodesofoperationsSinglewidthDoublewidthSerializes8 bits singlewidthscrambled 10 bits singlewidth8B 10B 16 bits doublewidthscrambled 20 bits doublewidth8B 10B LSBtransmittedfirstOptionalbitreversalsupportedPCSoutputrewired MSB LSB LSB MSB 37 TransmitterBuffer 38 Pre emphasisOpensEye 3 PCBTrace FR 4Material 40 PCBTrace FR 4Material Increasingpre emphasislevels 39 TransmitterCMU TXPLLblockCentralClockDividerBlockUsedonlyinbondedlane i e x4 modex8notsupportedinBasicmodeIndividualTXlocalCLKdividerblocks 40 TransmitterPLLBlock 2TransmistterPLLsREFCLKrange 50 622 08MHz ToTXLocalClockDividerBlocks ToTXLocalClockDividerBlocks ToCentralClockDividerBlock FromGlobalClockpins 41 CentralClockDividerBlock OneclockoutputperTransceiverBlockProvideshigh speedandslow speedclocksinx4 x8modesGenerateshigh speedclockfortransceiverblockSERDESGeneratesslow speedclockfortransceiverblockPCS 42 TransmitterLocalClockDividers OnedivideravailableperchannelProvideshigh speedandlow speedclocktoindividualchannelAllowsindividualchannelsintransceiverblocktorunatdifferentratesGenerateshigh speedclockforSERDESGeneratesslow speedclockforPCSDividestransmitterPLLoutputby1 2or4 43 AdditionalTransmitterBlocks ScramblerAppliespolynomialtodataEnsuresampletransitionssoclockcanbeextractedfromdataReducesEMIUsedwithandwithout8B 10BencodingExamplepolynomial PCIExpress x16 x5 x4 x3 1 ReceiverPath 45 ReceiverPath ExtractsclockfromserialdatastreamConvertsserialdatastreamtoparalleldataMustlocateandaligntobyteboundariesinserialstreamAccountforclockdifferencesinsource transmitter domainanddestination receiver domainIncreaseinnumberofblockswithgreatercomplexitythantransmitter 46 ReceiverPath ReceiverBlockDiagramReceiverPMAReceiverPCS 47 ReceiverBlockDiagram ToFPGA PhaseCompFIFO CentralBlock PowerDownandReset RecieverPLL ByteOrdering ByteDeserializer 8B 10BDecoder RateMatcher WordAligner Deserializer CRU PCS PMA 48 ReceiverPMABlocks ReceiverbufferReceiverPLLClockrecoveryunit CRU Deserializer 49 ReceiverInputBuffer On chipterminationCommon moderegenerationProgrammable adaptiveequalizationAC DCcouplingsupported PIPEmodeonly 50 ReceiverPLL UsedtotraintheCRUEachreceiverchannelcontainsitsownPLLProgrammablebandwidth 51 ReceiverPLL 52 ReceiverCRU RecoversclockfromserialinputdataFrequencytrainedbyreceiverchannelPLLMayalsobetrainedbytransmitterPLLGeneratesHigh speedclockfordeserializerLow speedclocksfortransceiver core 53 CRUFunctionalBlockDiagram 54 Deserializer TwomodesofoperationsSingle widthDouble widthDeserializes8 bits singlewidthscrambled 10 bits singlewidth8B 10B 16 bits doublewidthscrambled 20 bits doublewidth8B 10B LSBreceivedfirst 55 ReceiverPCSBlocks WordalignerRatematcher8B 10BdecoderBytedeserializerBytere orderingblockPhasecompFIFO 56 WordAligner WordAligner AlignstheserialdatawordboundaryProgrammablealignmentpatternAvailablesynchronizationstatemachineCannotbebypassed 57 WordAlignerBlocks Patterndetect detectswhenthealignmentpatterniswithinthecurrentwordboundaryAligner alignsthewordboundarytothealignmentpatternManualBitslip providesbarrelshiftertoalterwordboundaryRunlengthchecker detectsconsecutivebitvalues 58 SynchronizationStateMachine Provideshysteresisinlinkre synchronizationDetectsgoodcodegroupstodeterminesynchronizationDetectserrorstofalloutofsynchronization 59 ChannelAlignerBlock Deskew Alignsallchannelstochannel0clockExampleuse A initiatedsimultaneouslyonalllanesatthetransmitterChannelalignmentdonewhen4setsof A sarereceivedFallsoutofalignmentwhen4setsofmis alignedcolumnsof A sarereceived 60 RateMatcher ProvidesclockcompensationforasynchronoussystemsRemovesorinsertscharactersbasedonFIFOfilllevelsRatematcherautomaticallydeletesdatatopreventoverflowandinsertsK30 7topreventunderflowAvailableinsingleordoublewidthmodesProgrammableinsertanddeletecharactersAlsosupportedXAUI GigEandPCIeModes 61 RateMatcherDeletion BasicSingleWidth ProgrammablecommaandskipcharactersDefaultprogrammedcomma K28 5 andskip K28 0 ExampleshowsskipdeletionaftercommadetectionCandeleteanynumberofskipasnecessaryinSOS 62 8B 10BDecoder Converts10 bitcodegroupsto8 bitdataand1 bitcontrolindicatorAvailableinsingleanddoublewidthmodeDoublewidthmodeoperatesinaparallellinkedmodewithtwo8B 10BdecodersDete