Xilinx与ansoft合作写的一篇PI论文.pdf

Xilinx Corporation Ansoft Corporation Simultaneous Switching Output SSO Analysis Using Xilinx Virtex 4 FPGAs Goal Create a repeatable accurate and practical methodology for SSO analysis SSO and crosstalk discussion Xilinx package setup and crosstalk results Xilinx test board setup SSO measurement vs simulation results Overview Xilinx Virtex 4 FPGAs Laboratory measurements performed by Xilinx and Dr Howard Johnson Sigcon SSO is the noise due to several I O pins switching at the same time Induced voltage due to changing current in lead pins Simultaneous switching noise can be attributed to Poor signal to ground ratio Return path discontinuity The following factors can help contain SSO Avoid return path discontinuities Minimize total inductance of return path and keep it low On die decoupling capacitor strategy to cancel inductive noise SSO Description Ref BGA Crosstalk by Howard Johnson March 1 2005 Setup Schematic View or real representation BGA between PCB power and ground planes At time zero switches C and A drive LOW huge I O current transient Victim D will pick voltage glitch Vglitch SSO Simultaneous Switching Output Ref Intel Developer Forum by Richard Mellitz Crosstalk is the coupling of energy from one line to another Mutual capacitance electric field Mutual inductance magnetic field BOTH add to NEXT Near End crosstalk and FEXT Far End crosstalk The mutual inductance will induce current on the victim line opposite of the driving current Lentz s law Crosstalk General Overview Via field under BGA Primary coupling mode is inductive Magnitude of inductive crosstalk based on spatial arrangement and proximity of power and ground pins Current loops of aggressors and victim couple Inductive Crosstalk Ref BGA Crosstalk by Howard Johnson March 1 2005 Die and Package Scale Ref BGA Crosstalk by Howard Johnson March 1 2005 o o o o o o o o o o o o o o o o o FPGA Die 775um Bump 75um Pkg 10L 1068um Ball 500um height 700 um width PCB 22Layer 3125um 1 mm Ball Pitch Ref BGA Crosstalk by Howard Johnson March 1 2005 o o o o o o o o o o o o o o o o o 1 mm Ball Pitch 175 um Bump Pitch Signals Ground Plane Surface Vertical Region through bumps and metal layers very short distance 85 um very small mutual inductance Ground Plane Mutual Inductance Coupling Regions Ref BGA Crosstalk by Howard Johnson March 1 2005 o o o o o o o o o o o o o o o o o 1 mm Ball Pitch 175 um Bump Pitch Signals Ground Plane Surface Horizontal Region signal traces run close to ground plane Can be fairly long 14000 um Source of some mutual inductance from the neighboring traces contribution from other traces falls off rapidly Ground Plane Transmission Line Construction Via to Die Bump Mutual Inductance Coupling Regions Ref BGA Crosstalk by Howard Johnson March 1 2005 o o o o o o o o o o o o o o o o o 1 mm Ball Pitch 175 um Bump Pitch Signals Ground Plane Package Via Crosstalk Region This is a region of some mutual inductance coupling The total height in this area is approximately 1068 um Ground Plane Mutual Inductance Coupling Regions Mutual Inductance Coupling Regions Ref BGA Crosstalk by Howard Johnson March 1 2005 o o o o o o o o o o o o o o o o o 1 mm Ball Pitch 175 um Bump Pitch Signals Ground Plane PCB Via Crosstalk Region includes package balls printed circuit vias This is the primary problem area This is a region of significant mutual inductance coupling or via crosstalk The total height in this area is approximately 3635 um for a signal going all the way through a 22 layer PCB Ground Plane Ref BGA Crosstalk by Howard Johnson March 1 2005 Package Pinout O15LoadLoadGNDLoadLoadSPYSPYO15LoadLoadLoadGNDLoadLoadO25LoadLoadGNDclkoclkoLoadLoadO25GND GNDLoadLoadGNDLoadLoadLoadO15LoadLoadLoadGNDLoadO25LoadLoadLoadGNDLoadLoadLoadLoadO25LoadLoadLoadGND GNDLoadLoadLoadO15LoadLoadLoadLoadGNDLoadLoadLoadLoadO25LoadLoadLoadGNDLoadLoadLoadO25LoadLoadLoadGNDLoadclkoclko LoadLoadO15LoadLoadLoadGNDLoadLoadLoadO15LoadLoadLoadGNDLoadLoadO25SPYLoadGNDLoadLoadLoadLoadO25 LoadLoadLoadGNDLoadLoadO15LoadLoadLoadGNDLoadLoadLoadLoadO25LoadGNDSPYLoadLoadLoadO25LoadLoadLoadLoad LoadGNDLoadLoadLoadO15LoadAUXLoadLoadGNDLoadLoadLoadO25clkiAUXLoadLoadGNDLoadLoadLoadLoadO25LoadLoadLoadGNDLoadLoad LoadLoadLoadO15LoadLoadLoadGNDLoadLoadLoadLoadO25LoadLoadLoadclkiGNDINTINTO25LoadAUXLoadGNDLoadLoadLoadLoadO25 O15LoadLoadLoadGNDLoadLoadLoadLoadO15LoadLoadLoadSPYGNDLoadLoadLoadO25LoadAUXLoadLoadGNDLoadLoadLoadVDOLoadLoadLoad GNDLoadLoadLoadLoadO15AUXINTGNDLoadSPYINTO25LoadLoadINTGNDLoadLoadINTLoadO25clkoLoadLoadGNDclko LoadLoadLoadO15LoadINTLoadLoadGNDINTGNDINTLoadO25LoadLoadLoadGNDINTGNDINTLoadO25LoadLoadLoadLoadGDOLoadLoadSPY LoadO15LoadLoadLoadGNDLoadINTGNDINTGNDLoadLoadGNDLoadLoadINTGNDINTGNDAUXLoadLoadGNDLoadLoadLoadLoadO25SPY LoadLoadGNDLoadLoadSPYLoadO15LoadAUXGNDINTGNDINTclkiLoadLoadO25LoadINTGNDINTGNDLoadLoadLoadO25LoadLoadLoadLoadGND GNDLoadO15SPYAUXLoadLoadGNDLoadINTclkiO25LoadLoadLoadLoadGNDLoadLoadINTLoadO25LoadINTLoadLoadGND LoadLoadGNDLoadLoadLoadO15INTGNDINTGNDINTLoadO25LoadAUXLoadLoadGND GNDLoadO15LoadINTGNDINTGNDINTGNDAUXGNDO25LoadLoadLoadLoadGND GNDAUXLoadLoadGNDINTGNDINTGNDO25GNDINTGNDINTGNDGND GNDO25GNDAUXGNDVDIGDIINTGND GNDINTGNDINTGNDVDAGNDO25GND GNDGNDINTGNDINTGNDO25GNDINTGNDINTGNDLoadLoadAUXGND GNDLoadLoadLoadO33LoadAUXGNDINTGNDINTGNDINTLoadO25GND GNDLoadAUXLoadO33LoadLoadINTGNDINTGNDINTO25LoadLoadLoadLoadGNDLoadLoad GNDLoadLoadINTLoadO33LoadINTLoadGNDLoadLoadLoadclkiO25GNDINTLoadLoadGNDLoadLoadAUXLoadO25GND GNDLoadLoadLoadO33LoadLoadLoadGNDINTGNDINTLoadO25LoadINTclkiINTGNDINTGNDAUXO25LoadLoadLoadLoadGNDLoadLoadLoad SPYLoadO33LoadLoadLoadGNDLoadLoadAUXGNDINTGNDINTLoadLoadGNDLoadLoadGNDINTGNDINTLoadGNDLoadLoadLoadLoadO25 SPYLoadLoadLoadGNDLoadLoadLoadLoadO33LoadINTGNDINTGNDLoadLoadLoadO25LoadINTGNDINTGNDLoadINTLoadO25Loadclkoclko LoadGNDLoadLoadLoadO33INTLoadGNDINTLoadLoadSPYO25LoadINTLoadLoadGNDINTLoadAUXO25LoadLoadGNDLoad LoadLoadO33LoadLoadGNDLoadLoadAUXLoadO25LoadSPYLoadLoadGNDSPYLoadLoadLoadO25LoadLoadLoadLoadGNDLoadLoadLoadLoadO25 O33LoadLoadLoadGNDLoadAUXO33LoadINTLoadINTGNDclkiLoadLoadSPYO25LoadLoadGNDLoadLoadLoadLoadO25LoadLoadLoad LoadLoadGNDLoadLoadLoadLoadO33LoadLoadLoadGNDLoadLoadAUXclkiO25LoadLoadLoadGNDLoadLoadAUXLoadO25LoadLoadLoadGND LoadLoadLoadO33LoadLoadLoadGNDLoadLoadLoadO25LoadLoadLoadGNDLoadLoadLoadO25LoadLoadGNDLoadLoadLoad LoadO33LoadLoadLoadGNDLoadLoadLoadLoadO33LoadLoadLoadLoadGNDLoadLoadLoadLoadO25LoadLoadLoadLoadGNDLoadLoadLoadO25LoadLoad LoadLoadLoadGNDLoadLoadO33LoadLoadLoadGNDLoadLoadLoadO25LoadLoadLoadLoadGNDLoadLoadLoadLoadO25LoadLoadLoadGND GNDLoadLoadLoadO33LoadLoadLoadLoadGNDLoadLoadO25GNDGNDGNDLoadLoadLoadLoadO25LoadLoadLoadLoadGNDLoadGND GNDO33LoadLoadLoadGNDLoadLoadLoadO33LoadLoadGNDLoadclkoclkoO25SPYSPYLoadLoadGNDLoadLoadLoadO25 LoadGNDLoadLoad LoadLoadLoadVCCo VCCo LoadLoadLoad LoadLoadGNDLoad Unit Tile The LX60 FF1148 package is tessellated with a regular array of power and ground pins called a Sparse Chevron pattern 8 signals 1 power 1 ground min loop area Ref BGA Crosstalk by Howard Johnson March 1 2005 The Xilinx spiral test exercises 100 nearest neighbor aggressors in succession working around and around location A10 to increasingly distant locations SSN Function of Proximity Xilinx Virtex 4 FPGA and ML481 Test Board Setup and EM Simulation in SIwave Automated Setup and Simulation Xilinx System Overview 8 layer package on 24 layer test board Test points are at SMA connectors Spyholes Xilinx FPGA Virtex 4 LX60 FF1148 Package 8 layer flip chip BGA package Single Core 34 x 34 mm 1148 Balls 49 port simulation 40 IO 5 Spyhole IO 2 VCCO 9 2 Decaps AnsoftLinks It is a translator editor link from a 3rdparty layout tool to Ansoft environment Compatible with Cadence APD Allegro Mentor Boardstation PowerPCB Expedition Zuken CR5000 and Synopsys Encore Cadence Advanced Package Designer APD Access Ansoft Tools directly from APD Xilinx Virtex 4 FPGA Automation Step 1 SIwave Layer Stackup Create materials or Use Material Library Frequency Dependent Enter Information Layer Thickness Materials NOTE Sometimes proper stackup data is not in the layout tool SIwave Solderballs and Solderbumps Automatic Solderball Solderbump Generation SIwave Automated Grouped Nodes Automated Pin Grouping pins shorted for easy analysis Parts Pin and Net names preserved User can define region for grouping SIwave Automated Port Creation Assign ports by Pin names or Pin Groups Reference pins can be assigned by distance All Parts have imported pin names Package Ports Grouped References Die Side PortsBall Side Ports IO s VCCO 9 VCCO 9 and IO s of Interest NOTE The entire package structure is simulated to include all coupling SIwave Simulation Run Time ALL relevant couple structures are taken into account Fast interpolating sweep Total memory 800 MB Total Simulation Time less than 2 hours Designer with Nexxim Circuit is automatically created from SIwave results Each port becomes a sub circuit terminal Xilinx IBIS driver models are used as stimulus All lines properly terminated Aggressors sequentially added victim left quiet Xilinx Virtex 4 IBIS driver models ver 3 2 LVCMOS 2 5V 24 mA Fast Die SideBall Side Package Decaps Power Supply Crosstalk Analysis Setup in Nexxim Crosstalk Results Crosstalk analysis results vs number of aggressors Increase in number of aggressors will increase crosstalk Inductive crosstalk is dominating factor Crosstalk falls off quickly as you move the aggressor further and further from the victim Crosstalk Aggressor Proximity Aggressors progressively further from victim trace Xilinx ML481 Test Board Virtex 4 FPGA half of test board Board components included 24 layer FR4 Board 7 5 in x 20 in 28 Ports 23 IO ports 3 spyhole ports 1 VCCO 9 port 1 VRM port SIwave Ports at Ball Pads Board IO s of Interest L34 Spyhole Net Terminated IO s VDO Spyhole Net L34 Spyhole SMA VDO Spyhole SMA Terminations for Switched IO s ALL relevant couple structures are considered Fast interpolating sweep Total memory 1 GB Total Simulation Time less than 2 5 hours Board Simulation Profile SSO Simulation and Results Measurement vs Simulation SSO Analysis Setup in Nexxim Spyhole IO s held low at die Package Board Xilinx Virtex 4 IBIS drivers ver 3 2 LVCMOS 2 5V 24 mA Fast Simulation Mirrors Measurement Ref BGA Crosstalk by Howard Johnson March 1 2005 Measurement Setup Setup Worst case scenario Victim is kept at high or low Many I O s driven at the same time Inductive crosstalk received by I O s SSO Measured versus Simulated MeasuredSIwave Nexxim 125 MHz Clock 400 ps edge SSO Measured at L34 Spyhole SSO Measured versus Simulated MeasuredSIwave Nexxim 125 MHz Clock 400 ps edge SSO Measured at VDO Spyhole High Performance Design Solution Critical Elements needed to Converge Accuracy Capacity and Speed Time and Frequency Domain Robust Design Automation SIwave s Additional Capabilities Impedance Profile Measure Z11 Z21 etc for different locations Decoupling Analysis Change component values placement and measure Z change Resonant Mode Simulation Find Hotspots on your board Frequency Sweep Measure VRM effectiveness across board EMI EMC Analysis SIwave