时钟数据恢复电路英文文献.doc

Clock and Data Recovery CircuitAt the output of the limiting amplifier, the amplified data signal with sharpened data edges is available for further processing, but unique interpretation of the received signal requires timing information. Serial communication links do not provide a synchronization signal on a separate channel and therefore the receiver must rely on the extraction of the timing information from the data stream. This clock and data recovery process can be performed in a similar manner in optical communication, electrical serial links, hard drive read-out channels, as well as in some memory interfaces. In the latter field, advocates and opponents of the clock forwarding scheme still debate about the advantages and drawbacks of per-channel clock recovery circuits.Proper denomination of the whole synchronization process would be clock recovery and data retiming, better describing the behaviorally independent operations. Indeed the recovered clock is used to re-sample the incoming (or sometimes delayed) data to provide proper timing information, i.e. synchronicity, for the following blocks (Figure 8.1). However, in many implementations, the retiming operation is embedded in the clock recovery part to achieve improved circuit performance .FIGURE 8.1. Clock recovery and data retiming principle The major challenges of multichannel clock recovery circuit design have already been presented, namely, the achievement of low-power and low-area overhead with minimum impact on the circuit performance. First, an introduction to the important concepts in the design of clock recovery circuits is presented. Then, an overview of a variety of clock recovery topologies with their respective advantages and drawbacks allows the reader to fully understand the design choices operated later in this chapter. After discussion of appropriate topologies for multichannel clock recovery, a top-down design approach is presented which validates the jitter performance of the selected topology at the concept level, at the behavioral level and at the transistor level. Finally, the transistor-level design of the CDR is briefly discussed and characterization techniques are introduced.1.Clock Recovery Principles Historically, clock recovery was performed using resonant filter-based structures, either using discrete passive elements or resonant elements like surface acoustic wave (SAW) devices. In the era of systems-on-chip, requirements for small system form factors and minimum bill of material, the use of such off-chip components is strongly discouraged. In the long-haul market, where fiber-optic communications made their breakthrough first, phase-locked loop (PLL) topologies have become the mainstream solution, thanks to their capability of monolithic integration with a minimum number of external components, typically only one loop filter capacitor. Beyond the fact that the PLL currently still dominates the field and is the most well-known clock recovery topology, we would like to use this CDR structure as a basis to the explanation of some concepts to the novice reader. A more detailed discussion of PLL-based clock recovery circuits can be found in 83. For simplification, let us first consider a phase-locked loop with a periodic input signal (Figure 8.2). The three main building blocks are the phase detector (PD), the loop filter (LF) and the voltage-controlled oscillator (VCO). The phase detector compares the phase error between the input signal and the generated signal at the VCO output. The phase error is integrated in the low-pass loop filter and the resulting control signal tunes the VCO frequency, which in turn reduces the phase error.FIGURE 8.2. PLL with periodic input signal The periodic input signal f(t) can be written as the sum of sine and cosine functions, namely, its Fourier series: In most high data rate applications, we can neglect the higher order harmonics and focus on the fundamental signal, which can be written as: The instantaneous value f(t) of a sine wave is defined by its peak amplitude A and its instantaneous phase (t), which can again be decomposed into a constant angular frequency w0=2f0 and a time-varyin phase angle(t). In phase and frequency modulation schemes used in wireless data transmission, this time-varying phase angle contains the information to be transmitted. In fiber optic links, it does not contain any useful information, but represents the phase noise due to channel and circuit imperfections like noise and limited bandwidth. In both types of applications, the phase-locked loop technique allows to extract the time-dependent phase information and track the input signal. The in-phase output signal vout, locked to the input signal, guarantees a very small phase error e(t) between the input phase i(t) and the output phase o(t)。This situation is called phase lock. As frequency is the derivative of the instantaneous phase, constant phase error provides zero frequency error between input and output signals. The loop bandwidth being limited by the low-pass filter, these characteristics are not guaranteed for variations d(t)/dt at higher frequencies. As already mentioned, the two-level amplitude modulation of the carrier in serial links can lead to data runs which do not contain any transitions. The low-pass behavior of the loop filter allows the PLL to memorize the signal frequency during these long runs without loss of phase lock. The capture range defines the frequency span of the input signal for which phase lock can be achieved. For frequencies outside this span, the PLL will remain in a free-running situation. Lock range on the other hand defines the frequency span for which lock can be maintained once it is acquired. Without going into more details, these parameters depend on the characteristics of the PLL building blocks, among which the VCOs tuning range, defining the span of frequencies the oscillator can generate when driving its control voltage from one end to the other of the range.中文译文时钟及数据恢复电路在限幅放大器的输出端，与锐化的数据边缘的放大的数据信号是可用于进一步处理，但所接收的信号的独特的解释需要定时信息。串行通信链路不提供在一个单独的信道的同步信号，因此，接收器必须依赖于从数据流中的定时信息的提取。该时钟和数据恢复过程，可以以类似的方式进行，在光通信，电串行链路，硬盘驱动器读出的信道，以及在一些存储器接口。在后场，时钟传送方案的倡导者和反对者的辩论的优点和缺点，每个通道的时钟恢复电路。适当的面额为整个同步过程中，将时钟恢复和数据重定时，更好地描述行为独立操作。事实上，所恢复的时钟被用于重新采样传入的（或有时延迟）的数据，以提供适当的定时信息，即同步性，为下面的块（图8.1）。然而，在许多实施方式中，再定时操作被嵌入的时钟恢复部，以达到提高电路性能。图8.1 时钟恢复和数据重定时原则多通道的时钟恢复电路设计的主要挑战已经被提出，即实现对电路性能的影响最小的低功耗和小面积的开销。首先，介绍的时钟恢复电路设计中的重要概念。然后，概述的各种时钟恢复拓扑各自的优点和缺点，可以让读者充分了解操作将在本章后面的设计选择。讨论适当拓扑结构的多路时钟恢复后，自顶向下的设计方法，验证所选择的拓扑结构的概念，在行为层面，在晶体管级的抖动性能。最后，简要讨论的晶体管级设计的CDR和表征技术。1.时钟恢复原理从历史上看，使用谐振基于过滤器的结构，无论是使用分立的无源元件或类似的表面声波（SAW）器件的谐振元件执行时钟恢复。的系统级芯片的时代，小型系统的外形尺寸和最低物料清单的要求，这样的断片式元件的使用是强烈劝阻。在长途市场，其中光纤通讯，他们的突破，锁相环（PLL）的拓扑结构已经成为主流的解决方案，用最少的外部元件数量的单片集成的能力，通常只有一个循环滤波电容。除了PLL目前仍然占主导地位的领域，是最知名的时钟恢复拓扑，我们希望给新手阅读器使用CDR结构为基础的一些概念的解释。基于PLL的时钟恢复电路的更详细的讨论，在83中可以找到。为简化起见，让我们先考虑用一个周期性的输入信号锁相回路（图8.2）。的三个主要建筑块的相位检测器（PD），环路滤波器（LF）和压控振荡器（VCO）。的相位检测器的输