EDA正弦波发生器.pdf

正弦波发生器 正弦波发生器 1 设计要求 1 设计一个正弦波发生器 2 频率在 100Hz 1kHz 之间可调 调节的递增步进长度为 100Hz 3 输出电压峰峰值为 5V 4 每个信号周期取 32 个取样点 2 可选器件 EPM7128S 共阴极七段数码管 DAC0832 LM741 开关 电阻和电容 3 总体框图 控制电路 时钟信号 分频电路 防抖动电路 DAC0832 LM741 显示电路 图 正弦波发生器总体框图 4 功能简述 正弦波发生器输出 100Hz 1kHz 的正弦波 每按一次按键 频率增加 100hz 到 1khz 时 在恢复到 100Hz 依次循环 用示波器观测其输出波形 用数码管显示其频率值 将正弦波的一个周期波形进行 32 点幅度取样 用控制电路将各取样点的值顺序读出 送到 DAC 芯片 经过 D A 转换 得到的输出的电流值 再经 LM741 运算放大器 转换成 电压值 形成一个离散的正弦波信号 取样点愈多 离散正弦波的连续性越好 正弦波输出为 0 5V DAC0832 的参考电压选 5V DAC 输出的最大值为 255 11111111 最小值为 0 00000000 根据上面的分析将课题分成 5 个下层模块 即防抖动模块 显示分频模块 显示模块 和控制模块 5 源程序及注释 1 上层模块 上层模块 sin vhd library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity sin is port inf in std logic clk in std logic choose out std logic vector 3 downto 0 light out std logic vector 6 downto 0 dac out std logic vector 7 downto 0 end sin architecture structure of sin is signal clk100 temp std logic signal sel temp std logic vector 3 downto 0 signal clkfinal temp inf1 temp std logic signal reset1 temp std logic component keyin port inf in std logic clk in std logic inf1 out std logic end component component clkdiv100 port clk in std logic clk100 out std logic end component component count port inf1 in std logic clk in std logic clkfinal out std logic sel out std logic vector 3 downto 0 end component component display port clk100 in std logic sel in std logic vector 3 downto 0 choose out std logic vector 3 downto 0 light out std logic vector 6 downto 0 end component component circle port clkfinal in std logic dac out std logic vector 7 downto 0 end component begin u1 keyin port map inf clk inf1 temp u2 clkdiv100 port map clk clk100 temp u3 count port map inf1 temp clk clkfinal temp sel temp u4 display port map clk100 temp sel temp choose light u5 circle port map clkfinal temp dac end structure 2 下层模块 1 防抖模块 keyin vhd 下层模块 1 防抖模块 keyin vhd library ieee use ieee std logic 1164 all use ieee std logic signed all entity keyin is port clk in std logic inf in std logic inf1 out std logic end keyin architecture xiaodou of keyin is signal d1 std logic signal d2 std logic signal d std logic signal toutqu integer range 0 to 99999 signal clkqu temp std logic signal clkqu std logic begin process clkqu begin if clkqu event and clkqu 1 then d1 inf end if if clkqu event and clkqu 1 then d2 d1 end if d d1 and d2 end process inf1 d process clk begin if clk event and clk 1 then if toutqu 99999 then toutqu 0 else toutqu toutqu 1 end if if toutqu 49999 then clkqu temp 0 else clkqu temp 1 end if end if end process end xiaodou 2 显示分频模块 Clkdiv100 vhd 2 显示分频模块 Clkdiv100 vhd library ieee use ieee std logic 1164 all use ieee std logic signed all entity clkdiv100 is port clk in std logic clk100 buffer std logic end clkdiv100 architecture fenpin of clkdiv100 is signal tout100 integer range 0 to 2499 signal clk100 temp std logic begin p1 process clk begin if clk event and clk 1 then if tout100 2499 then tout100 0 else tout100 tout100 1 end if if tout100 1249 then clk100 temp 0 else clk100 temp 1 end if end if end process p2 process clk100 temp begin if clk100 temp event and clk100 temp 1 then clk100 not clk100 end if end process end fenpin 3 分频器模块3 分频器模块 Count vhd library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity count is port inf1 in std logic clk in std logic clkfinal out std logic sel out std logic vector 3 downto 0 end count architecture jishu of count is signal count10 integer range 0 to 9 signal clk temp std logic signal clkfinal temp std logic signal start integer range 0 to 156 signal tout integer range start to 156 begin process inf1 begin if inf1 event and inf1 0 then if count10 9 then count10 0 else count10selselselselselselselselselselstartstartstartstartstartstartstartstartstartstart 141 end case end process process clk begin if clk event and clk 1 then if tout 156 then tout start else tout tout 1 end if if tout 156 then clk temp 1 else clk temp 0 end if end if end process process clk temp begin if clk temp event and clk temp 1 then clkfinal temp not clkfinal temp end if end process clkfinal clkfinal temp end jishu 4 控制模块 circle vhd4 控制模块 circle vhd library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity circle is port clkfinal in std logic dac out std logic vector 7 downto 0 end circle architecture behavior of circle is signal count32 integer range 0 to 31 begin process clkfinal begin if clkfinal event and clkfinal 0 then if count32 31 then count32 0 else count32dacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdacdac 01100111 end case end process end behavior 5 显示模块 Display vhd 5 显示模块 Display vhd library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity display is port clk100 in std logic sel in std logic vector 3 downto 0 choose out std logic vector 3 downto 0 light out std logic vector 6 downto 0 end display architecture behavior of display is signal count4 integer range 0 to 3 begin p1 pro