cc1101的详解及单片机程序.doc

cc1101的详解及单片机程序 1.初始化SPI,MCU各引脚。 当有数据接收或发送状态声明时，有中断和查询两种方式。GDO0与GDO2引脚输出至MCU引脚，若要用中断则要接至MCU外部中断引脚，查询时则可用GPIO。 2.复位CC1101。 3.初始化CC1101。(写操作时可从SO中读出CC1101状态) 初始化后CC1100为IDLE状态. 4.状态机转换，写/读FIFO数据。 每次写操作时SO返回的值为写操作前的CC1100状态值，具体值见Table20；读状态命令为当前CC1100状态值，具体值见寄存器0X35说明；注意两者区别。 快速认识Cc1100 Cc1100可以工作在同步模式下，代价是：MCU自己控制前导码。本系统中，Cc1100将工作在异步模式下。 知识点 Head Byte：在 引脚 Cc1100.Csn 有效后，通过SPI总线写入 Cc1100的第一个字节。 Status Byte： 在写入 HeadByte 的同时，MCU 得到 Status Byte。 Burst Bit：在 Head Byte 中的一个 Bit, 有效值="1"，无效值="0" GDO0: GDO0可用作FIFO状态输出，载波感应(CS),时钟输出,GDO0 脚也能用作集成于芯片的模拟温度传感器(未用).配置寄存器为IOCFG0（0X02）,现在配置为RX模式下数据状态反应输出. GDO1: GDO1与SPI的SO共用引脚，默认状态下为3态，当CSn为低电平时，此引脚SPI的SO功能生效。配置寄存器为IOCFG0（0X01）,现在配置为空闲状态下3态，SPI模式下SO. GDO2: GDO2可用作FIFO状态输出，载波感应(CS）,时钟输出,配置寄存器为IOCFG0（0X00),现在配置为载波感应(CS）输出. TXOFF_MODE/RXOFF_MODE: 注意，此配置为在数据包被发送/接收后状态机状态决定位，仅是在发生发送或者接收后动作；当为IDLE时发SRX/STX后状态机不按此配置运行。TX/RX后要校准。 功率放大控制(PATABLE): 0X3E为功率写入地址，0X22为为功率配置寄存器。PATABLE 是一个8字节表，定义了8个PA 功率值。这个表从最低位（0）到最高位（7）可读和写，一次一位。一个索引计数器用来控制对这个表的访问。 每读出或写入表中的一个字节，计数器就加 1。当 CSn 为高时，计数值置为最小值。当达到最大值时，计数器由零重新开始计数。 FREND0.PA_POWER（2：0）从8个功率值中选择1个，且振幅为相应数等级。 异步模式: 在此模式下,CC1101中的MCU的若干支持机制会停用，包括数据包硬件处理，FIFO 缓冲,数据白化，交错(interleaver)和前向纠错(FEC) ，曼彻斯特编码(Manchester encoding); MSK不支持异步模式; PKTCTRL0.PKT_FORMAT = 3 使能异步模式，GDO0为input，GDO0, GDO1或GDO2为output 相应配置位为IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG IOCFG2.GDO2_CFG; 电磁波激活(WOR): 在WOR滤波使用之前RC振荡器必须启用，RC振荡器是 WOR 定时器的时钟源.在WOR下，收到信号后会自动进入RX模式. 载波感应(CS)与RSSI: 因此两配置相互有连系,所以一起论述. RSSI 只能在RX模式下才能有效,作用为对当前信号质量评估,信号质量可从RSSI寄存器读出.RSSI信号强度可从0X34取出. RSSI(信号强度)计算公式: 注:此为433M下,结果为负数, RSSI_dBm=(RSSI-256)/2-74 (RSSI;=128) RSSI_dBm= (RSSI/2)-74 (RSSI. 数据FIFO： 当TX操作时，由MCU控制，溢出时CC1101出错;当RX操作时，读空时CC1101出错 RX FIFO 和 TX FIFO 中的字节数也能分别从状态寄存器 RXBYTES.NUM_RXBYTES和TXBYTES.NUM_TXBYTES 中读出 4 位 FIFOTHR.FIFO_THR 设置用来控制FIFO 门限点 读单字节时，CSn继续保持低；。突发访问方式允许一地址字节，然后是连续的数据字节，直到通过设置 CSn 为高来断访问 当写操作时，最后一个字节被传送至 SI 脚后， 被 SO脚接收的状态位会表明在 TX FIFO中只有一个字节是空闲， 寄存器分类 Configration Registers 共47个，可读，可写 0x000x2E Status Registers 共14个，只读 0x300x3D Command Strobe 共14个，只写 寻址空间：0x300x3D 14个地址，对相应的地址进行写， 就相当于激活了对应的命令 本系统是用到的Strobe： CC1100_STROBE_RESET CC1100_STROBE_ENTER_RX_MODE CC1100_STROBE_ENTER_TX_MODE CC1100_COMMAND_STROBE_SIDLE CC1100_COMMAND_STROBE_SFRX TX FIFO 共64个，只写 RX FIFO 共64个，只读 Status(Command)Registers操作: 当地址为0X300X3D时 burst为1:对Status Registers的操作 Status Registers只可读，且只能一次读一个字节,不可写 burst为0:对Command Registers操作 寄存器的访问和一个寄存器的操作一样，但没有数据被传输.写完毕后,CC1100便执行相应操作. 读写FIFO，有两种模式：单字节读写；Burst读写。 单字节读写时序： 1 Cc1100.Csn有效。 2 写入Head Byte。 3 读、写一个1字节。 4 Cc1100.Csn无效。 #include ;#include ;#define INT8U unsigned char#define INT16U unsigned int#define WRITE_BURST 0x40 /连续写入#define READ_SINGLE 0x80 /读#define READ_BURST 0xC0 /连续读#define BYTES_IN_RXFIFO 0x7F /接收缓冲区的有效字节数#define CRC_OK 0x80 /CRC校验通过位标志/*sbit GDO0 =P13;sbit GDO2 =P32;sbit MISO =P16;sbit MOSI =P15;sbit SCK =P17;sbit CSN =P12;/*sbit LED2 =P34;sbit LED1 =P35;sbit KEY1 =P36;sbit KEY2 =P37;/*sbit led3=P23;sbit led2=P22;sbit led1=P21;sbit led0=P20;/*/INT8U PaTabel8 = 0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60;INT8U PaTabel8 = 0xc0 ,0xc0 ,0xc0 ,0xc0 ,0xc0 ,0xc0 ,0xc0 ,0xc0;/修改发射功率/*void SpiInit(void);void CpuInit(void);void RESET_CC1100(void);void POWER_UP_RESET_CC1100(void);void halSpiWriteReg(INT8U addr, INT8U value);void halSpiWriteBurstReg(INT8U addr, INT8U *buffer, INT8U count);void halSpiStrobe(INT8U strobe);INT8U halSpiReadReg(INT8U addr);void halSpiReadBurstReg(INT8U addr, INT8U *buffer, INT8U count);INT8U halSpiReadStatus(INT8U addr);void halRfWriteRfSettings(void);void halRfSendPacket(INT8U *txBuffer, INT8U size);INT8U halRfReceivePacket(INT8U *rxBuffer, INT8U *length);/*/ CC1100 STROBE, CONTROL AND STATUS REGSITER#define CCxxx0_IOCFG2 0x00 / GDO2 output pin configuration#define CCxxx0_IOCFG1 0x01 / GDO1 output pin configuration#define CCxxx0_IOCFG0 0x02 / GDO0 output pin configuration#define CCxxx0_FIFOTHR 0x03 / RX FIFO and TX FIFO thresholds#define CCxxx0_SYNC1 0x04 / Sync word, high INT8U#define CCxxx0_SYNC0 0x05 / Sync word, low INT8U#define CCxxx0_PKTLEN 0x06 / Packet length#define CCxxx0_PKTCTRL1 0x07 / Packet automation control#define CCxxx0_PKTCTRL0 0x08 / Packet automation control#define CCxxx0_ADDR 0x09 / Device address#define CCxxx0_CHANNR 0x0A / Channel number#define CCxxx0_FSCTRL1 0x0B / Frequency synthesizer control#define CCxxx0_FSCTRL0 0x0C / Frequency synthesizer control#define CCxxx0_FREQ2 0x0D / Frequency control word, high INT8U#define CCxxx0_FREQ1 0x0E / Frequency control word, middle INT8U#define CCxxx0_FREQ0 0x0F / Frequency control word, low INT8U#define CCxxx0_MDMCFG4 0x10 / Modem configuration#define CCxxx0_MDMCFG3 0x11 / Modem configuration#define CCxxx0_MDMCFG2 0x12 / Modem configuration#define CCxxx0_MDMCFG1 0x13 / Modem configuration#define CCxxx0_MDMCFG0 0x14 / Modem configuration#define CCxxx0_DEVIATN 0x15 / Modem deviation setting#define CCxxx0_MCSM2 0x16 / Main Radio Control State Machine configuration#define CCxxx0_MCSM1 0x17 / Main Radio Control State Machine configuration#define CCxxx0_MCSM0 0x18 / Main Radio Control State Machine configuration#define CCxxx0_FOCCFG 0x19 / Frequency Offset Compensation configuration#define CCxxx0_BSCFG 0x1A / Bit Synchronization configuration#define CCxxx0_AGCCTRL2 0x1B / AGC control#define CCxxx0_AGCCTRL1 0x1C / AGC control#define CCxxx0_AGCCTRL0 0x1D / AGC control#define CCxxx0_WOREVT1 0x1E / High INT8U Event 0 timeout#define CCxxx0_WOREVT0 0x1F / Low INT8U Event 0 timeout#define CCxxx0_WORCTRL 0x20 / Wake On Radio control#define CCxxx0_FREND1 0x21 / Front end RX configuration#define CCxxx0_FREND0 0x22 / Front end TX configuration#define CCxxx0_FSCAL3 0x23 / Frequency synthesizer calibration#define CCxxx0_FSCAL2 0x24 / Frequency synthesizer calibration#define CCxxx0_FSCAL1 0x25 / Frequency synthesizer calibration#define CCxxx0_FSCAL0 0x26 / Frequency synthesizer calibration#define CCxxx0_RCCTRL1 0x27 / RC oscillator configuration#define CCxxx0_RCCTRL0 0x28 / RC oscillator configuration#define CCxxx0_FSTEST 0x29 / Frequency synthesizer calibration control#define CCxxx0_PTEST 0x2A / Production test#define CCxxx0_AGCTEST 0x2B / AGC test#define CCxxx0_TEST2 0x2C / Various test settings#define CCxxx0_TEST1 0x2D / Various test settings#define CCxxx0_TEST0 0x2E / Various test settings/ Strobe commands#define CCxxx0_SRES 0x30 / Reset chip.#define CCxxx0_SFSTXON 0x31 / Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). / If in RX/TX: Go to a wait state where only the synthesizer is / running (for quick RX / TX turnaround). #define CCxxx0_SXOFF 0x32 / Turn off crystal oscillator.#define CCxxx0_SCAL 0x33 / Calibrate frequency synthesizer and turn it off / (enables quick start). #define CCxxx0_SRX 0x34 / Enable RX. Perform calibration first if coming from IDLE and / MCSM0.FS_AUTOCAL=1. #define CCxxx0_STX 0x35 / In IDLE state: Enable TX. Perform calibration first if / MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: / Only go to TX if channel is clear. #define CCxxx0_SIDLE 0x36 / Exit RX / TX, turn off frequency synthesizer and exit / Wake-On-Radio mode if applicable. #define CCxxx0_SAFC 0x37 / Perform AFC adjustment of the frequency synthesizer#define CCxxx0_SWOR 0x38 / Start automatic RX polling sequence (Wake-on-Radio)#define CCxxx0_SPWD 0x39 / Enter power down mode when CSn goes high.#define CCxxx0_SFRX 0x3A / Flush the RX FIFO buffer.#define CCxxx0_SFTX 0x3B / Flush the TX FIFO buffer.#define CCxxx0_SWORRST 0x3C / Reset real time clock.#define CCxxx0_SNOP 0x3D / No operation. May be used to pad strobe commands to two / INT8Us for simpler software. #define CCxxx0_PARTNUM 0x30#define CCxxx0_VERSION 0x31#define CCxxx0_FREQEST 0x32#define CCxxx0_LQI 0x33#define CCxxx0_RSSI 0x34#define CCxxx0_MARCSTATE 0x35#define CCxxx0_WORTIME1 0x36#define CCxxx0_WORTIME0 0x37#define CCxxx0_PKTSTATUS 0x38#define CCxxx0_VCO_VC_DAC 0x39#define CCxxx0_TXBYTES 0x3A#define CCxxx0_RXBYTES 0x3B#define CCxxx0_PATABLE 0x3E#define CCxxx0_TXFIFO 0x3F#define CCxxx0_RXFIFO 0x3F/ RF_SETTINGS is a data structure which contains all relevant CCxxx0 registerstypedef struct S_RF_SETTINGS INT8U FSCTRL2; /自已加的 INT8U FSCTRL1; / Frequency synthesizer control. INT8U FSCTRL0; / Frequency synthesizer control. INT8U FREQ2; / Frequency control word, high INT8U. INT8U FREQ1; / Frequency control word, middle INT8U. INT8U FREQ0; / Frequency control word, low INT8U. INT8U MDMCFG4; / Modem configuration. INT8U MDMCFG3; / Modem configuration. INT8U MDMCFG2; / Modem configuration. INT8U MDMCFG1; / Modem configuration. INT8U MDMCFG0; / Modem configuration. INT8U CHANNR; / Channel number. INT8U DEVIATN; / Modem deviation setting (when FSK modulation is enabled). INT8U FREND1; / Front end RX configuration. INT8U FREND0; / Front end RX configuration. INT8U MCSM0; / Main Radio Control State Machine configuration. INT8U FOCCFG; / Frequency Offset Compensation Configuration. INT8U BSCFG; / Bit synchronization Configuration. INT8U AGCCTRL2; / AGC control. INT8U AGCCTRL1; / AGC control. INT8U AGCCTRL0; / AGC control. INT8U FSCAL3; / Frequency synthesizer calibration. INT8U FSCAL2; / Frequency synthesizer calibration. INT8U FSCAL1; / Frequency synthesizer calibration. INT8U FSCAL0; / Frequency synthesizer calibration. INT8U FSTEST; / Frequency synthesizer calibration control INT8U TEST2; / Various test settings. INT8U TEST1; / Various test settings. INT8U TEST0; / Various test settings. INT8U IOCFG2; / GDO2 output pin configuration INT8U IOCFG0; / GDO0 output pin configuration INT8U PKTCTRL1; / Packet automation control. INT8U PKTCTRL0; / Packet automation control. INT8U ADDR; / Device address. INT8U PKTLEN; / Packet length. RF_SETTINGS;/const RF_SETTINGS rfSettings = 0x00, 0x08, / FSCTRL1 Frequency synthesizer control. 0x00, / FSCTRL0 Frequency synthesizer control. 0x10, / FREQ2 Frequency control word, high byte. 0xA7, / FREQ1 Frequency control word, middle byte. 0x62, / FREQ0 Frequency control word, low byte. 0x5B, / MDMCFG4 Modem configuration. /0xf6, / MDMCFG4 chang by allen 0xF8, / MDMCFG3 Modem configuration. /0x83, / MDMCFG3 chang by allen data rate = 2.398K 0x03, / MDMCFG2 Modem configuration. 0x22, / MDMCFG1 Modem configuration. 0xF8, / MDMCFG0 Modem configuration. 0x00, / CHANNR Channel number. 0x47, / DEVIATN Modem deviation setting (when FSK modulation is enabled). 0xB6, / FREND1 Front end RX configuration. 0x10, / FREND0 Front end RX configuration. 0x18, / MCSM0 Main Radio Control State Machine configuration. 0x1D, / FOCCFG Frequency Offset Compensation Configuration. 0x1C, / BSCFG Bit synchronization Configuration. 0xC7, / AGCCTRL2 AGC control. 0x00, / AGCCTRL1 AGC control. 0xB2, / AGCCTRL0 AGC control. 0xEA, / FSCAL3 Frequency synthesizer calibration. 0x2A, / FSCAL2 Frequency synthesizer calibration. 0x00, / FSCAL1 Frequency synthesizer calibration. 0x11, / FSCAL0 Frequency synthesizer calibration. 0x59, / FSTEST Frequency synthesizer calibration. 0x81, / TEST2 Various test settings. 0x35, / TEST1 Various test settings. 0x09, / TEST0 Various test settings. 0x0B, / IOCFG2 GDO2 output pin configuration. 0x06, / IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation. 0x04, / PKTCTRL1 Packet automation control. /0x05, / PKTCTRL0 Packet automation control. 0x01, /PKTCTRL0 crc disable chang by allen at 09.12.24 0x00, / ADDR Device address. 0x0c / PKTLEN Packet length. ;/*/函数名：delay(unsigned int s)/输入：时间/输出：无/功能描述：普通廷时,内部用/*static void delay(unsi