毕FPGA信号发生器业设计外文翻译.doc

FPGA-based signal processing for the LHCb silicon strip detectorsG. Haefeli, A. Bay and A. GongAbstractWe have developed an electronic board (TELL1) to interface the DAQ system of the LHCb experiment at CERN. Two hundred and eighty-nine TELL1 boards are needed to read out the different subdetectors including the silicon VEertex LOcator (VELO) (172k strips), the Trigger Tracker (TT) (147k strips) and the Inner Tracker (129k strips). Each board can handle either 64 analog or 24 digital optical links. The TELL1 mother board provides common mode correction, zero suppression, data formatting, and a large network interface buffer. To satisfy the different requirements we have adopted a flexible FPGA design and made use of mezzanine cards. Mezzanines are used for data input from digital optical and analog copper links as well as for the Gigabit Ethernet interface to DAQ.Keywords: LHCb; DAQ; FPGA; Gigabit Ethernet; Silicon strip detectors; Common mode; Zero suppression1. IntroductionThe LHCb 1 experiment at CERNs Large Hadron Collider (LHC) is dedicated to the studies of CP violation and rare decays in the “beauty” sector. For the DAQ interface an LHCb common readout board (TELL1) has been developed allowing to implement event synchronization, pedestal subtraction, Common Mode (CM) noise filtering, clusterization and network interfacing. In the following we give an overview of the LHCb DAQ architecture, a description of the TELL1 processor board and discuss the processing required for the LHCb silicon vertex detector (VELO) and by the silicon tracker detectors (TT and IT). LHCb has three levels of DAQ electronics, corresponding to the three levels of trigger called L0, L1 and High-Level Trigger (HLT). The L0 electronics is placed close to the detector and requires radiation-hard or radiation-tolerant components. To minimize the amount of electronics prone to the radiation effects, the L1 electronics is placed behind a shielding wall, quite far from the interaction point (more than 60m). To preserve synchronization over large distances LHCb has a global clock and fast signal transmission network, the Timing and Fast Control (TFC) 2, implementing the Timing and Trigger Control (TTC) devices developed at CERN 3. In particular, a radiation-hard chip (TTCrx 4) is placed on all frontend electronics to receive the system clock, trigger decisions, resets and special commands from the TFC. In turn the TFC is driven by the Readout Supervisor (RS) 5, responsible for scheduling the distribution of the trigger decisions. Finally, the overall DAQ is slow controlled by the Experiment Control System (ECS). The system overview is shown in Fig. 1. To cope with the radiation problem, the high density of detector channels, and the fast event rate L0 front-end ASICs have been developed. In particular, the Beetle front-end chip 6 will be used by the VELO, TT and IT. The frontend is required to send out L0 selected events in 900ns resulting in a maximal L0 accept trigger rate of 1.11MHz. Fig.1.LHCb trigger and data acquisition architecture.View Within ArticleAfter the L0 accept, the data are transferred by copper (VELO) or optical lines (all other detectors) to the counting houses where it is received by the TELL1 boards.2. TELL1 architectureFig. 2 shows a simplified block diagram of the TELL1 7 data flow. Physically the TELL1 is composed of a motherboard hosting several mezzanine cards. Its main processing elements are five large FPGAs. A description of each element is given below.Fig.2.Simplified block diagram of TELL1. The two options for optical and analog receiver cards are shown.A-Rx and O-Rx mezzanines: The analog version (A-Rx) receiver is employed for the reception and digitization of the VELO signals and the optical (O-Rx) for all other subsystems using optical links. Each one of the 4 A-Rx cards on the TELL1 provides 16 channels of 10-bit ADCs sampled at 40.078MHz resulting in a total of 64 10-bit receivers for the completely equipped board. On the other hand, each O-Rx card uses two connectors and implements a 12-way optical receiver resulting in a total of 24 channels per TELL1 board.PP-FPGA: Each one of the four “PreProcessor” FPGAs receives from the Rx cards its share of L0 accepted data over a parallel link at a maximal event rate of 1.11MHz.SyncLink-FPGA: The “Synchronization and Link” FPGA is connected to the TTCrx and distributes synchronization signals as clock, trigger and event identification to the PP-FPGAs. Moreover, it is in charge of collecting and merging the data fragments from the PP-FPGAs, to assemble multiple events into so-called multievent packets (MEPs), and to perform Ethernet and IP framing before transmission to the readout network.Quad Gigabit Ethernet (GBE): The readout network is interfaced by a four-port Gigabit Ethernet card 9 delivering 4Gbit/s data bandwidth.TTC: The TELL1 receives the fast control signals via the on-board TTC receiver chip TTCrx. Fast control signals are the clock (locked at 40.079MHz), the reset, the L0 trigger and the DAQ IP destination address.FEM mezzanine: The Front-end EMulator (FEM) is a Beetle front-end chip mounted on a small mezzanine card. It is connected with clock, reset and L0 trigger signals allowing to emulate the front-end electronics read-out timing.Throttle system: After zero suppression the event size is variable. Derandomizing buffers are employed to average the data rate and the data processing time. To prevent overflows, each buffer can generate a throttle signal acting on the trigger.ECS: The on-board slow control is managed with a commercial credit card-sized PC (CCPC) running a Linux kernel. A small adapter card, linked to the CCPC via PCI, provides all necessary interfaces to control and monitor all the other devices. The FPGAs and the quad Gigabit Medium Access Controller (GBE MAC) are on a shared microprocessor bus driven with a PCI bridge. I2C and JTAG is also provided for convenient programming of the FPGA firmware EEPROM and monitoring the devices. The disk-less CCPC is attached over the network to a boot server.3. Digital signal processingThe data arriving at the TELL1 can be affected by several kinds of noise and distortions. In particular, the long analog transmission line for the VELO can induce CM background and signal distortion induced by the finite frequency bandwidth of the cable. The PP-FPGA signal processing stages are shown in Fig. 3 (for details see Ref. 8). At reception the event synchronization is checked. For the VELO data processing a Finite Impulse Response (FIR) filter is foreseen to compensate for the long cable effects, followed by the pedestal subtraction. Pedestals are continuously calculated and updated. Several algorithms for CM correction have been studied and tested by mixing test beam data (supplying a model for the noise) and Monte Carlo events (the signal). The Linear CM Suppression (LCMS) algorithm 10 has become the baseline algorithm. The subsequent steps in the data processing are the zero suppression, data formatting and the assembly of multi-event packets (MEP) prior to transmission to the network.Fig. 3. Overview of the signal processing chain on the TELL1 board.The outlined processing requires simple arithmetic elements as adders, subtractors, accumulators and comparators as well as multiple memory access to load pedestals, thresholds and intermediate stored data. For the complete processing chain about 20 operations on mainly 8-bit numbers are required. With a total of 3k strips processed at 1MHz event rate, the required amount of arithmetic operations is 60Goperations/s per TELL1 board. The architecture of FPGAs with its distributed logic, arithmetic units and memories is very well suited for this task, allowing multiple pipelined processing. In a first step the input data are distributed over several identical processor channels each taking care of 64 detector physical channels. For the CM correction, the fixed event size allows the parallel processing to be scheduled synchronous for all channels and in addition makes the flow control simple. After the CM suppression, the data flow is derandomized in a buffer, capable to store 64 events. Derandomization is needed because the subsequent steps of clusterization and zero suppression need a processing time larger than the minimum spacing between L0 accepted events. In the chosen zero-suppression scheme clusters are formed among neighboring strips, the center position is encoded and the ADC values for all strips in a cluster are attached to the cluster information 11. The final step before transmission is the linking of the data from the different processor channels and the encapsulation in the required DAQ format. To cope with varying event size at the output to the Ethernet network, an external 2Mbyte large derandomizer buffer is attached to the SyncLink-FPGA. To reduce the Ethernet overhead, the event data are assembled in MEPs.4. ConclusionWe have developed the DAQ interface electronics for LHCb. The TELL1 board collects the data from the frontend, performs event synchronization, FIR filtering, pedestal following and subtraction, common mode suppression, zero suppression, data linking and interfacing to the Gigabit Ethernet readout network. The data processing is performed in four processor FPGAs accepting a total of 24 optical links running at 1.6Gbit/s or 64 channels of 10-bit at 40MHz for the analog version. Each processor FPGA provides a large amount of resources including 1.9Mbit on chip memory and embedded multipliers. The data path to the readout network is provided by four Gigabit Ethernet links providing 4Gbit/s output bandwidth.References1 S. Amato, et al. (LHCb collab.), “LHCb Technical Proposal” CERN/LHCC/1998-4, LHCC/P4, February 1998.LHCb reoptimized Detector Design and Performance Technical Design Report, LHCb, CERN LHCC 2003-030.2 Z. Guzik, R. Jacobsson, B. Jost, Driving the LHCb front-end readout, IEEE-Trans. Nucl. Sci. 51 (2004) 508.3 M. Ashton, et al., Status report on the RD12 project: timing, trigger and control systems for LHC detectors, CERN/LHCC 2000-002, LEB status report/RD12, 2000.4 J. Christiansen, A. Marchioro, P. Moreira, T. Toifl, TTCrx Reference Manual, CERN-EP/MIC, Geneva, Switzerland http:/ttc.web.cern.ch/TTC/TTCrx_manual3.10.pdf.5 R. Jacobsson, B. Jost, Z. Guzik, Readout supervisor design specifications, LHCb Note 2001-012.6 See URL: http:/wwwasic.kip.uni-heidelberg.de/lhcb/. Beetle 1.3 Reference Manual:（http:/wwwasic.kip.uni-heidelberg.de/lhcb/Publications/BeetleRefMan_v1_3.pdf. ）7 G. Haefeli, et al. TELL1 Specification for a common read out board for LHCb, IPHE Note 2003-002, http:/lphe.epfl.ch/publications/2003/iphe_03_002.pdf.8 G. Haefeli, Contribution to the development of the acquisition electronics for the LHCb experiment, CERN-THESIS-2004-036.9 H. Muller, A. Guirao, F. Bal, X. Tao, J. Christiansen, M. Muecke, N. Neufeld, G. Haefeli, Quad gigabit ethernet plug-in card, CERN EDMS https:/edms.cern.ch/file/520885/2/gbe_manual_ver2.pdf.10 A. Bay, G. Haefeli, P. Koppenburg, LHCb VeLo off detector electronics preprocessor and interface to the level 1 trigger, LHCb Note 2001-043.11 G. Haefeli, A. Gong, LHCb VELO and ST clusterization on TELL1, EDMS 690585, https:/edms.cern.ch/document/690585.基于FPGA信号处理的强子对撞硅片探测器摘要：在欧洲粒子物理研究所我们开发了一个用于连接大型强子对撞机实验的数据采集系统电子板(TELL1)。 二百八十九个电子板需要识别读出不同的辅助探测器，其中包括硅元素定位器(VELO) (172 k小条)，触发器跟踪仪(TT) (147 k小条)和内部追踪仪(129 k小条)。每个电子板都能处理64模拟或24数字化的光学链接。 电子主板提供共模矫正、零点抑制、数据格式编排和大型网络接口缓冲。我们采取一个灵活的FPGA设计并且利用夹层卡来满足不同的需求。夹层卡被应用于从数字式光学和模拟合金链接的数据输入和数据采集的千兆位网路卡接口。关键词：LHC（大型强子对撞机）；DAQ（数据采集）；FPGA（可编程门阵列）；千兆位网路卡接口；硅片探测器；共模；零点抑制1 简介在欧洲粒子物理研究所进行的大型强子对撞机实验致力于对完美象限仪中四角枕形失真和稀有衰退的研究。数据采集链接一个普通的大型强子对撞机识别电子板来执行事件同步、垫座差集、共模噪声过滤、群化和网络接口。接下来我们将会综述大型强子对撞机的数据采集构架， 描述电子板处理器并讨论强子对撞硅素跟踪仪探测器和追踪探测器（触发探测仪及信息探测仪）的处理需求。大型强子对撞机有三个水平的电子数据采集，对应于三个水平的触发器分别是初级、一级和高级触发器。初级电子被安置到探测器附近并且要求强辐射或抗辐射组分。 为使易受辐射作用的电子数量减到最小， 一级电子被安置在屏蔽墙之后，离互作用点(超过60 m)很远的地方。 要维持大型强子对撞机远程同步化则需要一个全局计时器和快速的信号传输网络、定时的迅捷网络控制 (TFC) 2，实施在欧洲粒子物理研究所被开发的定时触发控制设备(TTC)。 特别是，一块强辐射芯片被安置在所有电子高频端来接收系统时钟、触发器决策、重置和电路特殊命令。 反过来电路由解读员驱动并负责调度触发器决策的发布。 最后整体数据采集慢慢由实验控制系统控制。 系统综述如表一所示 。为处理辐射问题，开发了高密探测器通道和快速事件率初级结构化。特别是，前端凸出的芯片应用于追踪探测器、触发探测仪及信息探测仪。高频端在900 毫微秒内发出初级筛选事件导致初级触发率达到1.11兆赫的最大比率。图1.大型强子对撞触发器和数据采集构架View Within Article在初级触发器接收后，数据由追踪探测器或光学路径(其他探测器)被传送到会计室，由电子板接收。2电子板构架图2展示了一张简化的电子板数据流程方框图。从物理上说电子板是由一个母板托管几个夹层板构成。 它主要的处理部件是五大可编程门阵列。 如下给每个部件的描述。图2. 简化的电子板数据流程方框图，并显示两个光学和模拟接收板模拟接收器和光学接收器夹层： 模拟接收器用来接收和数字化追踪探测器的信号，光学接收器用来为其他子系统做光学链接。电子板上四个模拟接收器中的每一个提供10比特40.078兆赫ADCs 的16种渠道导致完全装置板共需64台10比特的接收器。 另一方面，每个光学接收器使用二个连接器并且实施12方式光学接收器导致每个电子板有24种渠道来接收。可编程门阵列的预处理器：模拟接收器上四个可编程门阵列的预处理器中的每一个初级接收数据并行链接触发率高达1.11兆赫。同步可编程门阵列： “同步和链接”的可编程门阵列连接到TTCrx同步信号作为定时和分配和触发活动的预处理鉴定。而且，它负责从FPGA的预处理器收集和合并数据碎片组装成所谓的并联数据包，在传输解读网络之前执行以太网和项目处理框架。 四千兆以太网(GBE)：解读网络是由一个四端口