带有高阻态选通和复位控制的四选一多路选择器.doc

带有高阻态选通和复位控制的四选一多路选择器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX41A ISPORT(A,B,C,D,RST,EN:IN STD_LOGIC;S1,S0:IN STD_LOGIC;Y:OUT STD_LOGIC);END ENTITY MUX41A;ARCHITECTURE ONE OF MUX41A ISSIGNAL S1S0:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINS1S0=S1&S0;PROCESS(RST,EN,S1S0)BEGINIF RST=1 THEN YYYYYY=NULL;END CASE;ELSE Y0);ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THEN QQ:=QQ+1; IF QQ=1111 THEN COUT=1; ELSE COUT=0 ; END IF;END IF;END IF;Q0);ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THEN QQ:=QQ-1; IF QQ=0000 THEN COUT=1; ELSE COUT=0; END IF;END IF;END IF;Q0);ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THEN IF UPDOWN=1 THEN QQ:=QQ+1; IF QQ=1111 THEN COUT=1; ELSE COUT=0 ;END IF; ELSE QQ:=QQ-1; IF QQ=0000 THEN COUT=1; ELSE COUT=0; END IF;END IF;END IF;END IF;Q=QQ;END PROCESS;END;带有并行置位的左移的八位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SHIFT_L IS PORT(CLK,LOAD: IN STD_LOGIC;DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);QB: OUT STD_LOGIC);END;ARCHITECTURE ONE OF SHIFT_L ISBEGINPROCESS(CLK,LOAD)VARIABLE REG8: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLKEVENT AND CLK=1 THEN IF LOAD=1 THEN REG8:=DIN; ELSE REG8(7 DOWNTO 1):=REG8(6 DOWNTO 0); END IF; END IF; QB=REG8(7); END PROCESS; END;Jk触发器library ieee;use ieee.std_logic_1164.all;entity jk isport(j,k,clk: in std_logic; q,nq: buffer std_logic);end;architecture behave of jk isbeginprocess(j,k,clk) variable q_r,nq_r:std_logic;beginif(clkevent and clk=1)thenif(j=0)and(k=1)thenq_r:=0;nq_r:=1;elsif (j=1)and(k=0)thenq_r:=1;nq_r:=0;elsif(j=1)and(k=1)thenq_r:=not q;nq_r:=not nq;end if;end if;q=q_r;nq=nq_r;end process;end;半减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY H_SUBER ISPORT(X,Y: IN STD_LOGIC;DIFF,S_OUT:OUT STD_LOGIC);END;ARCHITECTURE ONE OF H_SUBER ISSIGNAL XY,DS: STD_LOGIC_VECTOR( 1 DOWNTO 0);BEGINxy=x&y;DIFF=DS(1);S_OUTDSDSDSDSNULL;END CASE;END PROCESS;END;全减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F_SUBER ISPORT(X,Y,SUB_IN: IN STD_LOGIC;DIFFR,SUB_OUT:OUT STD_LOGIC);END;ARCHITECTURE ONE OF F_SUBER ISCOMPONENT H_SUBER PORT(X,Y: IN STD_LOGIC;DIFF,S_OUT:OUT STD_LOGIC);END COMPONENT;COMPONENT OR2A PORT(A,B: IN STD_LOGIC; C:OUT STD_LOGIC);END COMPONENT;SIGNAL A,B,C:STD_LOGIC;BEGINU1:H_SUBER PORT MAP (X=X,Y=Y,DIFF=A,S_OUT=B);U2: H_SUBER PORT MAP (X=A,Y=SUB_IN,DIFF=DIFFR,S_OUT=C);U3: OR2A PORT MAP (A=C,B=B,C=SUB_OUT);END;八位寄存器的左右可控寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SHIIFT_L_R ISPORT(CLK,LOAD,UD: IN STD_LOGIC;DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);QB: OUT STD_LOGIC);END;ARCHITECTURE ONE OF SHIIFT_L_R ISBEGINPROCESS(CLK,LOAD,UD)VARIABLE REG8: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLKEVENT AND CLK=1 THEN IF LOAD=1 THEN REG8:=DIN; ELSE IF UD=1 TH