ATmega16 毕业论文外文翻译.docx

外文原文The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATmega16 provides the following features: 16K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with com-pare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscil-lator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters,SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Inter-rupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/reso-nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-upcombined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmels high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effec-tive solution to many embedded control applications.The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,and evaluation kits.The interconnection between Master and Slave CPUs with SPI is shown in Figure 66.The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out Slave In,MOSI, line, and from Slave to Master on the Master In Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select,SS, line.When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use.When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.VS1003 is a single-chip MP3/WMA/MIDI audio decoder and ADPCM encoder. It contains a highperformance,proprietary low-power DSP processor core VS DSP4, working data memory, 5 KiB instruction RAM and 0.5 KiB data RAM for user applications, serial control and input data interfaces,4 general purpose I/O pins, an UART, as well as a high-quality variable-sample-rate mono ADC and stereo DAC, followed by an earphone amplifier and a ground buffer.VS1003 receives its input bitstream through a serial input bus, which it listens to as a system slave.The input stream is decoded and passed through a digital volume control to an 18-bit oversampling,multi-bit, sigma-delta DAC. The decoding is controlled via a serial control bus. In addition to the basic decoding, it is possible to add application specific features, like DSP effects, to the user RAM memory.(1)SPI BusesThe SPI Bus - that was originally used in some Motorola devices - has been used for both VS1003s Serial Data Interface SDI (Chapters 7.4 and 8.4) and Serial Control Interface SCI.(2)Data Request Pin DREQThe DREQ pin/signal is used to signal if VS1003s FIFO is capable of receiving data. If DREQ is high,VS1003 can take at least 32 bytes of SDI data or one SCI command. When these criteria are not met,DREQ is turned low, and the sender should stop transferring new data.Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without checking the status of DREQ, making controlling VS1003 easier for low-speed microcontrollers.Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should only be used to decide whether to send more bytes. It should not abort a transmission that has already started.Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1003 DREQ is also used to tell the status of SCI.(3) Serial Protocol for Serial Data Interface (SDI)The serial data interface operates in slave mode so DCLK signal must be generated by an external circuit.Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK .VS1003 assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or LSb first, depending of contents of SCI MODE.The firmware is able to accept the maximum bitrate the SDI supports.In VS1002 native modes (SM NEWMODE is 1), byte synchronization is achieved by XDCS. The state of XDCS may not change while a data byte transfer is in progress. To always maintain data synchronization even if there may be glitches in the boards using VS1003, it is recommended to turn XDCS every now and then, for instance once after every flash data block or a few kilobytes, just to keep sure the host and VS1003 are in sync.If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.For new designs, using VS1002 native modes are recommended.(4) Serial Protocol for Serial Command Interface (SCI)The serial bus protocol for the Serial Command Interface SCI (Chapter 8.5) consists of an instruction byte, address byte and one 16-bit data word. Each read or write operation can read or write a single register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes are always send MSb first.The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.Note: VS1003 sets DREQ low after each SCI operation. The duration depends on the operation. It is not allowed to start a new SCI/SDI operation before DREQ is high again.MP3 audio qualityFor MP3 is a lossy compression format, it offers a variety of different bit rate (bit rate) option - that is used to represent a second audio encoding data needed for the figures.Typical speed between 128 KBPS and 320 KBPS (kbit/s).In contrast, the CD on uncompressed audio bitrate is 1411.2 KBPS (16 / sample point x 44100 x 2 channel sampling HP/SEC).Using low bit rate coding MP3 file playback quality is usually low.Using low bitrate, the compress noise (compression will an artifact) (no) in the original recording will be presented during playback.A good example of compress noise is: the shout of compression;Because of its randomness and rapid change, so the encoder errors will be more obvious, and it sounds like echo.In addition to the code file bit rate;The quality of the MP3 file, also related to the quality of the encoder and the difficulty of the coded signal.Using high quality general signal encoder encoding, some people think that 128 kbit/s (MP3 and 44.1 kHz CD sampling sound similar to CD quality, at the same time get about now the compression ratio.Under the ratio of correct coding of MP3 can only get better sound quality than FM radio, this basically is the simulation of the medium bandwidth constraints, signal-to-noise ratio and other restrictions.Hearing tests, however, show the simple exercise test audience can reliably distinguish the difference between the 128 kbit/s (MP3 and original CD.In many cases they think MP3 sound quality is too low, is not acceptable, but some other audience or change the environment, such as in a noisy car) or the party they think the quality is acceptable.Obviously, the drawbacks of MP3 encoding on low-end sound CARDS or speakers are less obvious and high quality stereo in the connection to the computer system, especially when using the hi-fi equipment or high quality headphones is more obvious.中文翻译AVR 内核具有丰富的指令集和32 个通用工作寄存器。所有的寄存器都直接与算逻单元(ALU) 相连接，使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。这种结构大大提高了代码效率，并且具有比普通的CISC 微控制器最高至10 倍的数据吞吐率。ATmega16 有如下特点:16K字节的系统内可编程Flash(具有同时读写的能力，即RWW)，512 字节EEPROM，1K 字节SRAM，32 个通用I/O 口线，32 个通用工作寄存器，用于边界扫描的JTAG 接口，支持片内调试与编程，三个具有比较模式的灵活的定时器/ 计数器(T/C),片内/外中断，可编程串行USART，有起始条件检测器的通用串行接口，8路10位具有可选差分输入级可编程增益(TQFP 封装) 的ADC ，具有片内振荡器的可编程看门狗定时器，一个SPI 串行端口，以及六个可以通过软件进行选择的省电模式。 工作于空闲模式时CPU 停止工作，而USART、两线接口、A/D 转换器、SRAM、T/C、SPI 端口以及中断系统继续工作；掉电模式时晶体振荡器停止振荡，所有功能除了中断和硬件复位之外都停止工作；在省电模式下，异步定时器继续运行，允许用户保持一个时间基准，而其余功能模块处于休眠状态； ADC 噪声抑制模式时终止CPU 和除了异步定时器与ADC 以外所有I/O 模块的工作，以降低ADC 转换时的开关噪声； Standby 模式下只有晶体或谐振振荡器运行，其余功能模块处于休眠状态，使得器件只消耗极少的电流，同时具有快速启动能力；扩展Standby 模式下则允许振荡器和异步定时器继续工作。本芯片是以Atmel 高密度非易失性存储器技术生产的。片内ISP Flash 允许程序存储器通过ISP 串行接口，或者通用编程器进行编程，也可以通过运行于AVR 内核之中的引导程序进行编程。引导程序可以使用任意接口将应用程序下载到应用Flash存储区(Application Flash Memory)。在更新应用Flash存储区时引导Flash区(Boot Flash Memory)的程序继续运行，实现了RWW 操作。 通过将8 位RISC CPU 与系统内可编程的Flash 集成在一个芯片内， ATmega16 成为一个功能强大的单片机，为许多嵌入式控制应用提供了灵活而低成本的解决方案。ATmega16 具有一整套的编程与系统开发工具，包括：C 语言 编译器、宏汇编、 程序调试器/ 软件仿真器、仿真器及评估板。主机和从机之间的SPI 连接如Figure 66 所示。 系统包括两个移位寄存器和一个主机时钟发生器。通过将需要的从机的 SS 引脚拉低，主机启动一次通讯过程。主机和从机将需要发送的数据放入相应的移位寄存器。主机在SCK 引脚上产生时钟脉冲以交换数据。主机的数据从主机的MOSI 移出，从从机的MOSI 移入；从机的数据从从机的MISO 移出，从主机的MISO 移入。主机通过将从机的SS 拉高实现与从机的同步。配置为SPI 主机时， SPI 接口不自动控制 SS 引脚，必须由用户软件来处理。 对 SPI 数据寄存器写入数据即启动SPI 时钟，将8 比特的数据移入从机。传输结束后SPI 时钟停止，传输结束标志SPIF 置位。如果此时SPCR 寄存器的SPI 中断使能位SPIE 置位，中断就会发生。主机可以继续往SPDR 写入数据以移位到从机中去，或者是将从机的SS 拉高以说明数据包发送完成。最后进来的数据将一直保存于缓冲寄存器里。配置为从机时，只要SS 为高，SPI 接口将一直保持睡眠状态，并保持MISO 为三态。在这个状态下软件可以更新SPI 数据寄存器SPDR 的内容。即使此时SCK 引脚有输入时钟，SPDR 的数据也不会移出，直至SS 被拉低。一个字节完全移出之后，传输结束标志SPIF置位。如果此时SPCR寄存器的SPI中断使能位SPIE置位，就会产生中断请求。在读取移入的数据之前从机可以继续往SPDR 写入数据。最后进来的数据将一直保存于缓冲寄存器里。VS1003 是一个单片MP3/WMA/MIDI音频解码器和ADPCM编码器。它包含一个高性能，自主产权的低功耗DSP 处理器核VS_DSP4,工作数据存储器，为用户应用提供5KB 的指令RAM 和0.5KB 的数据RAM。串行的控制和数据接口，4 个常规用途的I/O 口，一个UART，也有一个高品质可变采样率的ADC和立体声DAC，还有一个耳机放大器和地线缓冲器。VS1003 通过一个串行接口来接收输入的比特流，它可以作为一个系统的从机。输入的比特流被解码，然后通过一个数字音量控制器到达一个18 位过采样多位- DAC。通过串行总线控制解码器。除了基本的解码，在用户RAM 中它还可以做其他特殊应用，例如DSP 音效处理。(1) SPI 总线SPI总线，最初被用在一些Motorola 器件上-也被应用于VS1003的串行数据接口SDI和串行控制接口SCI。(2) 数据请求脚 DREQDREQ 脚，在VS100