FPGA奇数和偶数分频器和半整数及任意小数分频器设计(Verilog程序).doc

Engineer LhraceAuthor:-Engineer Lhrace1、半整数分频占空比不为50%/说明：设计的史上最好用的半整数分频占空比不为50%，包含设计思路module div_5(clk,clk_div,cnt1,cnt2,temp1,temp2);/N+0.5input clk;output clk_div;output reg31:0cnt1,cnt2;output reg temp1,temp2;initial begin temp1=0;temp2=1;end /首先进行初始化，temp1=0;temp2=1parameter N=5; /设定分频系数为N+0.5always (posedge clk) /temp1上升沿跳变beginif(cnt1=2*N) /2*Nbegin cnt131:0=32d0;endelse begin cnt131:0=cnt131:0+32d1;endif(cnt1=32d0) begin temp1=1;end /高电平时间为N+1;if(cnt1=N+1) begin temp1=0;end /低电平时间为N;endalways(negedge clk) /temp2下降沿跳变beginif(cnt2=2*N) /2*Nbegin cnt231:0=32d0;endelse begin cnt231:0=cnt231:0+32d1;endif(cnt2=32d0) begin temp2=0;end /低电平时间为N;if(cnt2=N) begin temp2=1;end /高电平时间为N+1;endassign clk_div=temp1&temp2; /逻辑与endmodule /如果要进行N+0.5分频/思路：总的来说要进行N+1+N=2N+1次分频/在时钟的上升沿和下降沿都进行跳变/上升沿进行占空比为N+1比N的时钟temp1;/下降沿进行占空比为N比N+1的时钟temp2;/最后div=temp1&temp2 即可得到所需要的半整数分频分频5.5仿真结果2、奇数分频占空比为50%/说明：奇数分频。module div_5(clk,clk_div,cnt1,cnt2,temp1,temp2);/input clk;output clk_div;output reg31:0cnt1,cnt2;output reg temp1,temp2;parameter N=5; /设定分频系数always (posedge clk)beginif(cnt1=N-1) /N-1进行N计数begin cnt131:0=32d0;endelse begin cnt131:0=cnt131:0+32d1;endif(cnt1=32d0) begin temp1=1;end /if(cnt1=(N-1)/2) begin temp1=0;end /当计数到(N-1)/2时翻转endalways(negedge clk)beginif(cnt2=N-1) /N-1begin cnt231:0=32d0;endelse begin cnt231:0=cnt231:0+32d1;endif(cnt2=32d0) begin temp2=1;end /;if(cnt2=(N-1)/2) begin temp2=M)begin pk-1:0=pk-1:0-M+N;delete=1b0;endif(pM) begin pk-1:0=pk-1:0+N;endif(N=p&pM)begin delete=1b1;endendalways(delete)/删除脉冲，相当于合并脉冲beginif(delete=1)clkout=1;elseclkout=clk;endreg cnb;wire cnc;output divclk;assign cnc=cnb&clk;assign divclk=!cnc&clkout;always (posedge clk)begin if(delete=1)cnb=1;else cnb=0;endendmodule /output reg 5:0cnt1,cnt2; /cnt1,cnt2用于验证脉冲是否准确/always (posedge clk)/begin /if(cnt1=M-1)/cnt1=0;/else cnt1