三电平铁电存储器.doc

本科毕业设计（论文）外文参考文献译文及原文 学 院 自动化学院 专 业 电子信息科学与技术 年级班别 2008级（1）班 学 号 3204006666 学生姓名 林晴 指导教师 徐迎棚 2008年 6 月目录三电平铁电存储器的研究1摘要.11 简介22 二进制FeRAM操作33 FeRAM三电平信号操作64 参数多元化建模9AN INVESTIGATION INTO THREE-LEVEL FERROELECTRIC MEMORY10Abstract101. Introduction112. Binary FeRAM Operation134. Modeling Parameter Variations20三电平铁电存储器的研究摘要铁电随机存取存储器是一项新型非易失性存储器技术，比起闪存它有几个关键优点，包括能允许更多次的“编程擦除”操作和更快速写入速度。然而，当前FeRAM阵列的存储容量落后于闪存存储器三个数量级以上；因此，铁电随机存取存储器到目前为止更趋向于小应用程序的应用，例如智能卡和电子计量。FeRAM存储密度的显著增长依赖于许多前沿技术的进展。大部分数字存储器技术工艺使用两个可能的数据信号电平将每个存储单元编码为1位。多电平存储单元型闪存存储器使用4个数据信号电平来增加存储密度，每个存储单元编码为2位。在这篇文章中我们研究了使用3个数据信号电平来增加存储密度的可能性的初步调查研究结果，使之从每单元1位增加到平均每单元1.5位。这个问题主要挑战是确保三个信号状态的精确写入（极化方向分别为上、下的极化了的铁电薄膜，和去极化的薄膜）和在存在噪声以及不可避免的器件参数变化的情况下，存储单元状态的可靠检测。关键词：铁电存储器 多电平信号 三电平信号 三电平存储器 多电平存储单元1 简介FeRAM是一种非易失性存储器新型技术，该存储器有几个重要优点凌驾于以往闪存存储器之上。例如，闪存存储单元能够编程和擦除最多106次，然而现在铁电存储单元最少可循环编程擦除1012次。而且，闪存存储单元要求相关复杂的序列需数百毫秒才能完成而在FeRAM存储单元编写则精确到50纳秒之内。铁电存储单元更大的优点是能够在低压电源运行（例如小于或等于1.8伏）和它们能够用两个额外的掩模综合到标准的互补金属氧化物半导体技术。闪存存储器相关编程和擦除需要就比较大的电压（例如10伏），这需要在芯片上进料泵和耐高电压配电网。而且，闪存存储单元需要第二层多晶硅来形成可编程浮动门和薄隧道屏障一律产物。FeRAM的最近发展缩放和联合工艺能为植入到FeRAM高密度系统芯片成功介绍而铺路。闪存存储器设备，尽管已经可在多吉比特设备密度中应用，然而FeRAM最主要设备只需在一百万兆密度就可应用。与非易失性技术的长时间相比，闪存存储器得益于产品的多电平研究与开发投资。FeRAM存储密度的增加将会要求FeRAM存储单元更小型化的发展、参考电压和单元信号感觉电路的改进，并且更好理解和铁电材料必需的道具长期稳定性的控制。在这篇文章我们介绍以仿真为基础的初步研究结果，即可能使用三电平信号增加FeRAM存储单元存储密度的调查研究。铁电材料非线性偏振特性，例如钛酸铅锆这种材料使它实现用与多级闪存存储器的4级信号是非常困难的，因此我们考虑使用3电平信号代替，3个存储单元状态是通过铁电薄膜在向上方向及向下方向之间的振动，而且没有偏振网络通过铁电薄膜。如果每个存储单元能够存储三个状态之一，因而一对存储单元就能够存储9个不同联合状态。这些状态中只有8个是被要求来编码这3位的，意味平均每个存储单元1.5位的存储密度。（一个这样的编码以前在阿尔伯达大学动态随机存取存取器多级实验中使用过）转换和来自外部二进制信息三进制价值的有序偶能被轻易完全应用在外围设备组合逻辑。文章剩余部分由以下部分组成：第二部分回顾了FeRAM的传统二进制运算体系，而第三部分则描述被提议FeRAM的三进制算法的操作，第四部分描述FeRAM晶体管器件不可避免参数变化的三重操作在我们的仿真研究中产生怎样的影响。第五部分则概述研究的结果，最后，第六部分做了一些总结性评论。2 二进制FeRAM操作FeRAM定义具有这种特性的材料为铁电体，这种可逆的剩余饱和电极化强度材料能够通过外电场对铁电物质产生影响。这中偏振行为好像出现在电介质负极表面正极信号稳定电源的地方。电介质这样行为被描述为磁滞回线，如图1中线1.铁电薄膜从偏振下方出发落在滞后回线的点A上。当正外电场向上方向时，铁电介质的单个显微域的偏振就会开始使它们自己更适应这个领域。在绕过磁滞回线大半圈后到达B点，矫顽电磁场力矩想那样到达，如果外在电场撤走，电介质的剩余极化强度网络将会消失，即是电介质会被极化。另一方面，施加电场大于矫顽力C时，铁电介质的正向极化逐渐达到饱和极化值Ps，撤走外电场会导致上面的电滞回线下至点D，即Pr剩余极化强度向上相应的点。外电场反方向的脉冲调制导致磁滞回线从点D穿过点E再到点F然后回到点A。图1 铁电磁滞回线特性 传统的二进制FeRAM使用磁滞回线上的A到D相应的剩余极化强度来存储二元数值，我们任意假设点A和点D被用来分别编码二元数值“1”和“0”，（在我们提议的三电平FeRAM，第三种状态在典型的极化起源将会是极化状态。这个和点A和点B相对应的状态在此时将不会被简单译成“1”和“0”，在后面会详细介绍）。FeRAM生产使用一个二元件设计。线2表现的单管单容的元件设计与传统的动态随机存取存储器元件非常相似。主要不同是用铁电薄膜代替电介质储能电容器（例如PZT），而电容器的低接线端则由转辙器垫板线性信号驱动而不是保持常电压（例如1/2VDD）。当在动态随机存取存储器元件，元件状态是由放大器电路线性字节和进入电子晶体管微软公司生产的文字处理软件控制开关读出（不是自动显示）。读出放大器是快速微分模式比较电路仪，该电路仪能快速测出元件信号和产生的合适的基准信号之间的势差信号。图2中线2（b）容量更大的双管双容的元件设计，这个元件设计的主要优点是能够自我参考：即两个字节线性信号BL架桥装置和BLN，它们被连接到进位补充信号的元件能被读出放大器直接比较而无需产生分别的参考信号。双管双容由于大概2倍强度的电荷设计提供更强运作，大概以二等分存储容量为代价。图2铁电存储器单管单容和双管双容的设计原理图 下图3显示了涉及FeRAM单管单容单元的读操作的关键波形，首先动波形BL通过控制信号PRE预先充电至0伏。当PRE信号为0时，BL被孤立且留在0伏浮。逻辑地址解码器接收到行地址并将其解码，然后在WL线上相应的地方置1.这将电容器上部节点的存储单元连接到BL线上。在这一结果发生后，PL线受到脉冲影响电压从0伏升至电源正极提供的电伏数VDD。因为铁电电池电容器在设计的时候依大小排列所以如果极化一开始与外电场相反的，则PL信号会导致单元的极化发生转变。如果初始极化与PL产生的场是一致的，则当外电场作用时极化强度出现轻微增长，但是保留原来的方向。在极化方向相反的情况下，相关大的正电荷由于大部分铁电分子的极化转变而跳转到BL上，标志存储为“1”；否则是没有铁点存储单元极化逆转和出现在BL上的比较小正电荷标志存储“0”。BL基准信号可能是期望值“0”到“1”之间的某一个潜在值，与BL的基准信号相比，BL信号在这个点上仍然是相对较弱，所以它必须通过微分感应放大器来放大信号。所需参考信号有几种不同产生方法。图3铁电存储单元破坏性读入操作波形因为检测存储状态“1”的操作会将该单元的极化状态改变为“0”状态所以记录读入操作是破坏性的，(对于存储状态为“0”的情况，极化方向保持不变)。同DRAM的读入操作一样，每个FeRAM存储单元的读写操作是后面必须伴随一个回复原始数据的操作（否则会被写操作写入的新数据所代替），这个回复操作是通过PL回到0伏而BL保持震荡幅度的最大值这个简单操作来完成的。参考图1中的点，跟随回复“1” 随后的“1”对应追踪磁滞回线从A点到C点（对PL施加脉冲，转换存储单元极化然后判断BL）然后追踪F线上（即回复到“1”）最后回到A（留下储存状态“1”）。 判断“0”包括磁滞回线从D到C点上的线（对PL施加脉冲而没有改变存储单元极化和对BL的判断）然后停在C上（即回写“0”）而后回到D点（留下状态“0”）。图4中显示了BL上预期“0”信号和“1”信号的分布状态，因为铁电电荷极化转变的出现，“1”信号分布在较高的电压区，而“0”信号不会在该区出现。那两个分布区域几乎是一样的（如果进行设当的规格化），但“1”信号区域趋向有一个较大的变化，因此有一个较低的概率密度。图4二进制铁电随机存取存储器BL信号分布状态3 FeRAM三电平信号操作多电平信号的操作要求在写操作期间产生精确存储数据信号（也就是极化状态），而精确的二进制线性参考检测信号在读操作器件产生。另外，为了使噪声信号比率在判断过程中达到信号的最大值，使用广域意义上的数字信号是非常重要的。多电平FeRAM存储单元的一个更大的挑战是铁电磁滞特性的非线性，该特性使控制电介质的剩余极化强度变得非常困难.由于以上这些原因，我们选择重新使用两个同样的非零剩余极化强度作为传统的二进制FeRAM存储单元（它已经不是再是简单地编码成“0”和“1”）然后以增强去极化为条件作为第三个存储单元存储状态。我们将这三个状态分别表示为“L”（代替“0”状态）“M”和“H”（代替“1”状态）图5显示了电压分布状态，当判断这三个存储单元存储状态时其中有一个状态值是预期产生的。M的中间分布状态出现自新的极化状态。为了使三电平信号能够进行确定的编码工作，L和H之间分布状态必须有个一个十分大的间隙（例如大约100毫伏）。当然，L和M分布状态之间、M和H分布状态之间必须有一个十分大的噪声边缘，否则，将会出现判断错误。图5 铁点随机存储器三重信号BL电压分布状态正如早期描写的那样，成对存储单元的多电平信号认为是与成对存储单元平均3字节存储容量一起产生的（也就是存储容量是1.5字节/单元）。下面分别表示了各种可能的编码。被提议的三电平信号铁电随机存取存储器存在着许多挑战。在传统的二进制FeRAM中，L和H信号能用同样的方式分别被写成0和1信号，但是在回写步骤期间，M信号要求FeRAM存储单元必须有一个快速充分的极化方式。正如图3所示，一个L仅仅通过驱动BL到0伏而PL被驱动到VDD来回写到一个存储单元。当PL被回复0伏而BL被控制在VDD时H的值回写到存储单元上，M级的写操作将会是更加复杂的操作。为了完全擦除先前存储单元状态，另一个中药的挑战是当PL被驱动为VDD时BL首先被置0（正如被回写到L上一样）。然后PL被允许转回0伏而BL被保持在0伏。最后，BL需要被驱动到一个强制性电压即+VM,这个电压的绝对值小于VDD的值。VM的大小刚好足够BL电源被变弱回0之后录制一个0剩余极化强度。因此BL电路需要被驱动三个电压值，即0伏，正VDD和正VM，前面两个驱动电压要求电子晶体管转变成两个低电阻电源节点。VM则由第三个控制补给电压提供，或者由VDD稳定反馈放大动力提供。这些驱动程序就所有可能转载的数据来说需要求反馈以确保在BL上产生一个精确的VM值。存储单元住装载的改变决定于在入门行有多少个存储单元需要被写为M值。下图6中显示了当三个信号写操作时铁电磁滞回线的轨迹，图6显示了L线怎样从所有三个原始状态写下的过程。图6显示了H写操作过程轨迹，最后图6还显示M值是怎样被写的。记录在水平线上被截磁滞特性的steepness（也就是在被强制的电压值上）意味着VM的错误能导致在最后剩余极化强度发生错误（它的理想值是0）图6 三重信号铁电随机存储器的写操作过程三电平信号的FeRAM的读操作能用连续或者与关于两个线性参考字节电压检测信号比较，即Vref_H和Vref_L。Vref_L被定位于L和M信号之间的分布区域，反之Vref_H被定位于M和H信号分布区域之间。在连续的判断中，存储单元信号首先和Vref_L比较，然后再和Vref_H信号比较（反之亦然）。在并行判断中，每个存储单元存储信号必须被复制，然后复制信号同时和相应的Vref_L 和Vref_H信号比较。连续判断允许同样的读出放大器被用于同步判断中，但是必须以更长的读操作为代价。三电平FeRAMVref_L 和Vref_H匹配信号的产生相比之下要比传统的二进制铁电存储器Vref信号的产生要困难得多。判断过程中的复杂性是在破坏性的判断伴随正反馈的情况下每个存储单元创造多级信号必须的（典型的情况是传统的读出放大器）。一种被成功应用于多电平动态随机存取存储器的方法是通过把每个位线划分成两个或更多等电容的子位线来复制存储单元信号。在三电平信号FeRAM中，存储单元电荷能首先倾卸两个连接的子位线上，然后这两个存储单元的复制信号能通过打开电子晶体管开关来产生。4 参数多元化建模在面对三电平FeRAM的只要调整中是确保三个信号状态的精确描写，就好像这个存储单元状态的可靠判断，即使晶体管不可参数变化的出现被传入生产过程中。因为涉及很多不同的参数所以整个过程是非常复杂的，而精确的参数分布状态数据是不能共用的。为了使用我们初步的研究可行，我们依赖于中心界限定理和假设许多不同参数变量能被联合录制在一个正常分布式的有效的电容器元件尺寸上。我们的目标是因此变成是确定怎样坚固地控制有效元件尺寸变化的总数以确保BL信号上可靠判断上有足够的噪声容量（例如至少是100毫伏）。我们使用由Rickes发展的铁电电容器模型并假设（为了方便）的来自台湾半导体制造业有限公司的0.35微米互补金属氧化物半导体是逻辑过程。Rickes模型要求设置几个不通的参数。例如为了录制图5中的结构我们设置存储单元A区域等于0.65平方微米，PZT的铁电厚度d=170纳米，相关的电介质常量 =350，剩余极化强度Ps = 30 C/cm2，正极外加电压VCP = 1.5 V,负极外加电压VCN = -1.5 V,而电容器单位漏电阻Rleak = 5 K/cm2.这些值就好像参数程序总是能适应任何实际程序。部分图好像图5通过首先BL信号和元件尺寸之间以在L、M和H状态存储单元开始的决定关系而获得的一部分图，图7通过模拟存储单元容量加上线性电路（如在图2中）使用如上面一样的电解槽模型参数且假设典型的线性电容为300 fF。存储单元区是关于表面价值的大范围扫描所以存储单元信号结果分布状态建立到后面去。图7相对于细胞区域的BL电压AN INVESTIGATION INTO THREE-LEVEL FERROELECTRIC MEMORYAbstractFerroelectric random-access memory (FeRAM) is an emerging nonvolatile memory technology that has several key advantages over flash memory, including much greater program-erase endurance and much faster write speed. However, FeRAM array storage capacities currently lag behind those of flash memory by more than three orders of magnitude; consequently, FeRAM has so far tended to be used only in niche applications, such as smart cards and electronic metering. Significant increases in FeRAM storage density will require progress on many technical fronts. Most digital memory technologies use two possible data signal levels to encode one bit per storage cell. Multilevel cell flash memory uses four data signal levels to increase the storage density to two bits per cell. In this paper we report the results of a preliminary study that investigated the possibility of using three data signal levels to increase the array storage density from 1 bit per cell to an average of 1.5 bits per cell. The principal challenge is to ensure the accurate writing of the three signal states(ferroelectric film polarized in the “up” and “down” directions, and a depolarized film) and the reliable sensingof cell states in the presence of noise and inevitable device parameter variations.Keywords:ferroelectricmemory, multilevelsignaling, ternary signaling, ternary memory, multilevel cells.1. IntroductionFerroelectric random-access memory (FeRAM) is an emerging technology for nonvolatile memory (NVM) that has several important advantages over mainstream flash memory 1. For example, flash memory cells can be programmed and erased at most 106 times whereas the endurance of FeRAM cells is now at least 1012 program-erase cycles 2. Also, flash memory cells require relatively complex write sequences that can take hundreds of milliseconds to complete whereas FeRAM cells can be written deterministically in under 50 ns. Further advantages are that FeRAM cells can be operated using a low power supply voltage (e.g. 1.8V) and they can be integrated into a standard CMOS technology using as few as two extra masks 3. Flash memory requires relatively large program and erase voltages (e.g. 10 V) that require on-chip charge pumps and high-voltage-tolerant distribution networks. Also, flash memory cells require a second layer of polysilicon, to form the programmable floating gates, and the creation of a uniformly thin tunneling barrier. Recent progress in FeRAM scaling and process integration could pave the way for the successful introduction of embedded FeRAM into high-density Systems-on-a-Chip (SoCs) 3.Flash memory devices, however, are already available in multi-gigabit device densities whereas the largest FeRAM parts are available only in 1 megabit densities 4. As the long-time incumbent NVM technology, flash memory benefits from massive levels of research and development investment. Increases in FeRAM storage density will require much furtherprogress on FeRAM cell miniaturization,improvements inreference voltage generation and cell signal sensing circuitry, and better understanding and control of the long-term stability of the properties of the required ferroelectric materials.In this paper we present the results of a preliminary simulation-based study that investigated the possibility of using three-level (i.e., ternary) signaling to increase the storage density of FeRAM cells 5. The nonlinear polarization characteristic of ferroelectric materials, such as lead zirconium titanate (PZT), makes it very difficult to implement the four-level signaling that is used in multilevel cell (MLC) flash memory. Instead, we considered the use of three-level signals, where the three cell states are (1) polarization in the “up” direction across the film, (2)polarization in the opposite “down” direction across thefilm, and (3) no net polarization across the film (i.e., a suitably depolarized film). If each cell can store one of three states, then pairs of cells can store nine distinct joint states. Only eight of those states are required to encode three bits, implying an average storage density of 1.5 bits per cell. (Such an encoding has been used previously in experimental multilevel DRAMs at the University of Alberta 6,7.) The translation to and from external binary information to ordered pairs of ternary values can be readily accomplished using combinational logic in the peripheral circuitry.The rest of this paper is organized as follows: The next section reviews conventional binary FeRAM operation, while section 3 describes the operation of the proposed ternary FeRAM. Section 4 describes how the effects on ternary FeRAM operation of inevitable device parameter variations were modeled in our simulation study. Section 5 summarizes the results of that study. Finally, section 6 makes some concluding remarks.2. Binary FeRAM OperationFeRAM exploits a defining property of a class of materials, called ferroelectrics, in which a reversible remanent electric polarization can be imposed on the ferroelectric by applying an external electric field. The polarization behaves like regions of immobile charge of opposite sign that appear on opposite surfaces of the dielectric. The behaviour of a ferroelectric is described by a hysteresis loop, like the one shown in Figure 1. A ferroelectric film could start out with a “down” remanent polarization Pr at point A in the loop. When a positive external field is applied in the “up” direction, the polarizations of the individual microscope domains of the ferroelectric start to re-orient themselves to be more aligned with that field. After traveling up along the lower branch of the loop to point B, a coercive electric field strength +Ec is reached such that, if the field were to be removed, there would be no net remanent polarization in the dielectric; that is, the dielectric would be left depolarized. If, on the other hand, the applied field is increased further in strength to point C, the degree of polarization in the dielectric reaches a saturation value +Ps. Removing the applied field then causes the upper branch of the hysteresis loop to be followed down to point D, which corresponds to an “up”remanent polarization of +Pr. Pulsing the external electric field in the opposite direction causes the loop to be traced from point D through to points E to F and then back to A.Fig. 1 Ferroelectric Hysteresis Loop CharacteristicConventionalbinary FeRAMuses theremanent polarizations corresponding to points A and D on the hysteresis loop to store the two binary values. We will arbitrarily assume that points A and D are used to encode binary values “1” and “0”, respectively. (In our proposed ternary FeRAM, the third state will be the depolarized state at the origin of the polarization characteristic. The states corresponding to points A and D would then no longersimply encode “1” and “0”, as will be explained later.) Production FeRAMs use one of two cell designs. The 1T-1C cell design, shown in Figure 2(a), is very similar to a conventional DRAM cell. The major differences are that the storage capacitor dielectric is replaced with a thin film of ferroelectric (e.g. PZT), and that the “lower” terminal of the capacitor is driven by a switched plate line (PL) signal instead of being held at a constant plate potential (e.g. VDD). As in a DRAM cell, the state of the cell is sensed by a sense amplifier circuit (not shown) via a bit line (BL) and an access transistor switch controlled by a word line (WL). The sense amplifier is a fast differential-modecomparator circuit that rapidly determines the sign of the potential difference between the cell signal and an appropriately generated reference signal. Figure 2(b) shows the bulkier 2T-2C cell design. The advantage of this cell is that it is self-referencing: the two bitline signals, BL and BLN, that are connected to the cell carry complementary signals that can be compared directly by the sense amplifier, with no need for a separately generated reference signal. The 2T-2C design offers more robust operation, due to the roughly double-strength signal charge, at the cost of a roughly halved storage density.Fig. 2 1T-1C and 2T-2C FeRAM Cell DesignsFigure 3 shows the key waveforms that are involved in a read operation to a 1T-1C FeRAM cell. First, BL is precharged to 0 V by asserting control signal PRE. When PRE is de-asserted, BL is isolated and left floating at 0 V. Address decoder logic receives the row address, decodes it,and asserts high the corresponding WL. This connects the“upper” (storage) node of the cell capacitor to BL. After this event, the PL is pulsed from 0 V up to the positive supply voltage VDD. The ferroelectric cell capacitor is sized during design so that the PL signal will cause the polarization of the cell to be switched if the polarization is initially opposed to the applied field. If the initial polarization increases in strength slightly when the field is applied, but retains the same direction. In the case of a polarization reversal, a relatively large positive charge is dumped onto BL due mostly to the switched ferroelectric polarization, indicating a stored “1”; otherwise, there is no polarization reversal in the cell ferroelectric and a smaller positive charge appears on the BL indicating a stored “0”. The BL signal is still relatively weak at this point, so it must be amplified by a differential-mode sense amplifier that compares the BL signal with a reference BL signal that is midway in potential between the expected “0” and “1” BL signals. There are various ways of generating the required reference signal 1.Note that the read operation is destructive because the act of sensing a stored “1” changes the polarization state of the cell to a “0” (for a stored “0” the polarization direction remains unchanged). Read operations to an FeRAM cell must therefore be followed by a write back operation that restores the original data (or substitutes newly written data for a write operation), in the same way as in a DRAM read operation. A write back is accomplished by simply returning the PL back to 0 V with the BL held at the amplified full-swing value. Referring to the points in Figure1, sensing a “1” followed by writing back a “1” corresponds to tracing through the loop from A to C (pulse the PL, switch the cell polarization, and sense the BL), then to F (write back the “1”), and then back to A (leave a stored “1”). Sensing a “0” involves tracing through the loop from D to C(pulse the PL without switching the cell polarization and sense the BL), then stay at C (write back the “0”), and then back to D (leave a stored “0”).Fig. 3 Destructive Read Operation in Binary FeRAMFig. 4 BL Signal Distributions in a Binary FeRAM 8Figure 4 shows the distribution of the expected “0” and “1” signals on the BL 8. The “1” signal distribution is higher in voltage because of the presence of the switched ferroelectric charge, which is absent in the “0” signal. The areas of the two distributions will be the same (if properly normalized) but the “1” distribution will tend to have a greater variance, and hence a lower peak probability density, than the “0” distribution 3.3. Ternary FeRAM OperationMultilevel signal operation requires the creation of accurate stored data signals (i.e., polarization states) during write operations, and the creation of accurate reference bitline signals for sensing during read operations. In addition, to maximize the signal-noise-ra