quartus经典时序分析器优先级3.doc

Default Multicycle Hold timing assignment Specifies the default value for the Multicycle Hold requirement (that is, the minimum number of clock cycles required before a register latches a value). The Default Multicycle Hold requirement is overridden on specific nodes by any individual Multicycle Hold requirements. This is an advanced assignment that can be changed by typing the following command at the Quartus II Tcl Console window:set_global_assignment -name default_hold_multicycle The following describes the settings for this assignment: Same as MulticycleSpecifies that the Default Multicycle Hold requirement should match the value of the Multicycle requirement. This setting is less restrictive than the One setting and generally produces fewer hold time violation warnings. Same as Multicycle is the default value for this setting. OneSpecifies that the signal should latch on the final edge. This setting is more restrictive than the Same as Multicycle setting; however, it is sometimes the default setting used by other timing analysis tools. Figures 1 and 2 below illustrate the impact of the Same as Multicycle and One assignment settings. Figure 1. Same As MulticycleFigure 2. OneClock Enable Multicycle timing assignmentAllows you to relax the setup relationship of all enable-driven registers of the assigned pin or register by specifying the number of destination clock cycles required before the enable-driven register latches a value. In other words, the Clock Enable Multicycle assignment assigns a Multicycle value to all enable-driven registers fed by the assigned register or pin.For example, assigning an Clock Enable Multicycle value of 2 to a single register delays the latch edge by one destination clock cycle on every enable-driven register of the assigned register or pin, even if the source and destination registers are not controlled by the same clock enable.Similarly, assigning a point-to-point Clock Enable Multicycle requirement affects all register to register paths in which the source and destination registers feed an enable-driven register.However, if you want to assign a Clock Enable Multicycle only to paths in which both the source and destination registers are controlled by the same clock enable signal, then you must specify a point-to-point assignment in which the enable-driving register is both the source and destination of the assignment.You can assign the Clock Enable Multicycle timing assignment between a specific source and destination. Wildcard and assignment group assignments are not supported for this assignment. By default, the Classic Timing Analyzer assumes that the Default Multicycle Hold setting is the same as the Multicycle setting. Therefore, if you assign a Multicycle, Source Multicycle, Enable Multicycle, or Clock Enable Source Multicycle assignment, the corresponding hold requirement is similarly changed unless you specify a specific value for the hold requirement. 文章来源：重心网络 版权所有The following table prioritizes each legal assignment type, and shows which paths are affected when assigned. Priority 1 assignments take precedence over priority 2 assignments, and so on. Within a priority level, the most stringent requirement takes precedence. Specifying a point-to-point Clock Enable Multicycle assignment may increase the time necessary for timing-driven compilation.Priority LevelAssignment Type/LocationAffected Path(s)1Point-to-point assignment from register to register.Point-to-point assignment from input or bidirectional pin to register.Point-to-point assignment from pin to pin.All register to register paths in which the source and destination registers directly feed an enable-driven register.2Single-point assignment to any register or pin.All enable-driven registers directly fed by the assigned register or pin.Clock Enable Source Multicycle timing assignmentAllows you to relax the setup relationship of all enable-driven registers of the assigned pin or register by specifying the maximum number of source clock cycles required before an enable-driven register latches a value. In other words, the Clock Enable Source Multicycle assignment assigns a Source Multicycle value to all enable-driven registers fed by the assigned register or pin.For example, assigning an Clock Enable Source Multicycle value of 2 to a single enable register overrides the setup relationship by delaying the latch edge by one clock cycle on every enable-driven register of the assigned register, even if the source and destination registers are not controlled by the same clock enable.Similarly, assigning a point-to-point Clock Enable Source Multicycle requirement affects all register to register paths in which the source and destination registers feed an enable-driven register.However, if you want to assign a Clock Enable Source Multicycle only to paths in which both the source and destination registers are controlled by the same clock enable signal, then you must specify a point-to-point assignment in which the enable-driving register is both the source and destination of the assignment.You can assign the Clock Enable Source Multicycle timing assignment between a specific source and destination. Wildcard and assignment group assignments are not supported for this assignment. The value of this assignment must be a positive number greater than zero. By default, the Classic Timing Analyzer assumes that the Default Multicycle Hold setting is the same as the Multicycle setting. Therefore, if you assign a Multicycle, Source Multicycle, Clock Enable Multicycle, or Clock Enable Source Multicycle assignment, the corresponding hold requirement is similarly changed unless you specify a specific value for the hold requirement.The following table prioritizes each legal assignment type, and shows which paths are affected when assigned. Priority 1 assignments take precedence over priority 2 assignments, and so on.