在线可编程技术笔试选题—(答案—题目1-8).doc

宁波大学科学技术学院made in 501EDA FPGA VHDL程序-T1-library ieee;use IEEE.STD_LOGIC_ARITH.ALL;ENTITY wav_gen isport(clk:IN STD_LOGIC;to_DA:out std_logic_vector(9 downto 0);END wav_gen;ARCHITECTURE archi OF wav_gen IScomponent lcnt isport(clock: in std_logic; q: out std_logic_vector (9 downto 0);end component;component lrom isport(address: in std_logic_vector (9 downto 0); q: out std_logic_vector (9 downto 0);end component;beginsignal cou_add: std_logic_vector(9 downto 0);U1:lcnt port map(clk,cou_add);U2:lrom port map(cou_add,to_DA);end architecture archi;-T2-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY adder4b ISPORT(CIN:IN STD_LOGIC;A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC);END ENTITY adder4b;ARCHITECTURE BEHAV OF adder4b ISSIGNAL SS,AA,BB:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGINAA=0&A;BB=0&B;SS=AA+BB+CIN;S=SS(3 DOWNTO 0);COUT=SS(4);END ARCHITECTURE BEHAV;-T3-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;ENTITY f_adder isport(ain,bin,cin:IN STD_LOGIC;cout,sum:out std_logic);END f_adder;ARCHITECTURE archi OF f_adder IScomponent H_ADDER isport(a,b: in std_logic;co,so: out std_logic);component H_ADDER;beginsignal co_int1,co_int2,so_int: std_logic_vector(9 downto 0);U1:H_ADDER port map(ain,bin,co_int1,so_int);U2:H_ADDER port map(so_int,cin,co_int2,sum);cout=co_int1 and co_int2;end architecture archi;-T4-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MUX_if ISPORT(SEL,AIN,BIN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); COUT:OUT STD_LOGIC_VECTOR(1 DOWNTO 0)END ENTITY MUX_if;ARCHITECTURE BEHAV OF MUX_if ISSIGNAL CC:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINprocess(SEL)beginIF SEL=00 THENCC=AIN OR BIN;ELSIF SEL=01 THENCC=AIN AND BIN;ELSIF SEL=10 THEN CC=AIN XOR BIN;ELSIF SEL=11 THENCC=NOT AIN;ELSE CC=00;END IF;COUTCCCCCCCC CC=00;END CASE;COUT=CC;END PROCESS;END ARCHITECTURE BEHAV;-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MUX_WHEN_ELSE ISPORT(SEL,AIN,BIN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); COUT:OUT STD_LOGIC_VECTOR(1 DOWNTO 0)END ENTITY MUX_WHEN_ELSE;ARCHITECTURE BEHAV OF MUX_WHEN_ELSE ISSIGNAL CC:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINCC=AIN OR BIN;WHEN SEL=00ELSEAIN AND BIN;WHEN SEL=01ELSEAIN XOR BIN; WHEN SEL=10ELSENOT AIN;WHEN SEL=11ELSE00;COUTLED7SLED7SLED7SLED7SLED7SLED7SLED7SLED7SLED7SLED7S NULL;END CASE;END PROCESS;END ARCHITECTURE one;-T6-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder3x8 ISPORT(G1,G2:IN STD_LOGIC;AIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); YOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY decoder3x8;ARCHITECTURE BEHAV OF decoder3x8 ISSIGNAL YY:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(G1,G2,AIN)BEGINIF G1=0 AND G2=0 THENCASE AIN ISWHEN 000=YYYYYYYYYYYYYYYY=11111110;END CASE;ELSE YY=11111111;END IF;END PROCESSEND ARCHITECTURE BEHAV;-T7-library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use IEEE.STD_LOGIC_ARITH.ALL;ENTITY CNT10 isport(RESET,LD,CLK,UPDN:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);CABO:OUT STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END CNT10;ARCHITECTURE archi OF CNT10 ISbeginprocess(CLK,RESET,LD,UPDN,DIN) VARIABLE Q_OUT:STD_LOGIC_VECTOR(3 DOWNTO 0);beginif(RESET=0) THENQ_OUT:=0000;CABO=0;ELSIF(RISING_EDGE(CLK) THENif LD=0 THENQOUT:=DIN;ELSEif(UPDN=1)thenIF(Q_OUT=1001) THENQ_OUT:=0000;CABO=1;ELSE Q_OUT:=Q_OUT+1;CABO=0;END IF;ELSEIF(Q_OUT=0000) THENQ_OUT:=1001;CABO=1;ELSE Q_OUT:=Q_OUT-1;CABO=0;END IF;END IF;END IF;END IF;Q=Q_OUT;END PROCESS;END ARCHITECTURE archi;-T8-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity odd_div isport(fin :in std_logic; din:in std_logic_vector(3 downto 0); fout:out std_logic);end entity odd_div;architecture behav of odd_div issignal N: integer;signal cnt:int