STM32的嵌套中断系统NVIC详细整理.doc

STM32 的嵌套中断系统 本文档由“风中的叶”整理；QQ：654705188一、综述： 1、STM32 (Cortex-M3) 中的优先级概念 STM32(Cortex-M3)中有两个优先级的概念：抢占式优先级和响应优先级，也把响应优先级称作“亚优先级”或“副优先级”，每个中断源都需要被指定这两种优先级。1. 何为占先式优先级(pre-emption priority) 高占先式优先级的中断事件会打断当前的主程序/中断程序运行抢断式优先响应，俗称中断嵌套。2. 何为副优先级(subpriority) 在占先式优先级相同的情况下，高副优先级的中断优先被响应； 在占先式优先级相同的情况下，如果有低副优先级中断正在执行， 高副优先级的中断要等待已被响应的低副优先级中断执行结束后才能得到响应非抢断式响应(不能嵌套)。3. 判断中断是否会被响应的依据 首先是占先式优先级，其次是副优先级； 占先式优先级决定是否会有中断嵌套； Reset、NMI、Hard Fault 优先级为负(高于普通中断优先级)且不可调整。4. 优先级冲突的处理 具有高抢占式优先级的中断可以在具有低抢占式优先级的中断处理过程中被响应，即中断的嵌套，或者说高抢占式优先级的中断可以嵌套低抢占式优先级的中断。 当两个中断源的抢占式优先级相同时，这两个中断将没有嵌套关系，当一个中断到来后，如果正在处理另一个中断，这个后到来的中断就要等到前一个中断处理完之后才能被处理。如果这两个中断同时到达，则中断控制器根据他们的响应优先级高低来决定先处理哪一个；如果他们的抢占式优先级和响应优先级都相等，则根据他们在中断表中的排位顺序决定先处理哪一个。5. Cortex-M3中对中断优先级的定义 既然每个中断源都需要被指定这两种优先级，就需要有相应的寄存器位记录每个中断的优先级；在Cortex-M3中定义了8个比特位用于设置中断源的优先级，这8个比特位可以有8种分配方式，如下：所有8位用于指定响应优先级最高1位用于指定抢占式优先级，最低7位用于指定响应优先级最高2位用于指定抢占式优先级，最低6位用于指定响应优先级最高3位用于指定抢占式优先级，最低5位用于指定响应优先级最高4位用于指定抢占式优先级，最低4位用于指定响应优先级最高5位用于指定抢占式优先级，最低3位用于指定响应优先级最高6位用于指定抢占式优先级，最低2位用于指定响应优先级最高7位用于指定抢占式优先级，最低1位用于指定响应优先级这就是优先级分组的概念。6. stm32中对中断优先级的定义 Cortex-M3允许具有较少中断源时使用较少的寄存器位指定中断源的优先级，因此STM32把指定中断优先级的寄存器位减少到4位，这4个寄存器位的分组方式如下： 第0组：所有4位用于指定响应优先级第1组：最高1位用于指定抢占式优先级，最低3位用于指定响应优先级第2组：最高2位用于指定抢占式优先级，最低2位用于指定响应优先级第3组：最高3位用于指定抢占式优先级，最低1位用于指定响应优先级第4组：所有4位用于指定抢占式优先级 AIRC(Application Interrupt and Reset Register)寄存器中有用于指定优先级的 4 bits。这4个bits用于分配preemption优先级和sub优先级，在STM32的固件库中定义如下:/* Preemption Priority Group */#define NVIC_PriorityGroup_0 (u32)0x700) /* 0 bits for pre-emption priority 4 bits for subpriority */#define NVIC_PriorityGroup_1 (u32)0x600) /* 1 bits for pre-emption priority 3 bits for subpriority */#define NVIC_PriorityGroup_2 (u32)0x500) /* 2 bits for pre-emption priority 2 bits for subpriority */#define NVIC_PriorityGroup_3 (u32)0x400) /* 3 bits for pre-emption priority 1 bits for subpriority */#define NVIC_PriorityGroup_4 (u32)0x300) /* 4 bits for pre-emption priority 0 bits for subpriority */ 可以通过调用STM32的固件库中的函数NVIC_PriorityGroupConfig()选择使用哪种优先级分组方式，这个函数的参数有下列5种：NVIC_PriorityGroup_0 = 选择第0组NVIC_PriorityGroup_1 = 选择第1组NVIC_PriorityGroup_2 = 选择第2组NVIC_PriorityGroup_3 = 选择第3组NVIC_PriorityGroup_4 = 选择第4组 接下来就是指定中断源的优先级，下面以一个简单的例子说明如何指定中断源的抢占式优先级和响应优先级：/ 选择使用优先级分组第1组NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);/定义的结构体变量NVIC_InitTypeDef NVIC_InitStructure;/ 使能EXTI0中断NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQ;NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; /指定抢占式优先级别1NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; / 指定响应优先级别0NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;NVIC_Init(&NVIC_InitStructure);/ 使能EXTI9_5中断NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQ;NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; /指定抢占式优先级别0NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; / 指定响应优先级别1NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;NVIC_Init(&NVIC_InitStructure);- 要注意的几点是： 1. 如果指定的抢占式优先级别或响应优先级别超出了选定的优先级分组所限定的范围，将可能得到意想不到的结果； 2. 抢占式优先级别相同的中断源之间没有嵌套关系； 3. 如果某个中断源被指定为某个抢占式优先级别，又没有其它中断源处于同一个抢占式优先级别，则可以为这个中断源指定任意有效的响应优先级别。 2、开关总中断 在STM32/Cortex-M3中是通过改变CPU的当前优先级来允许或禁止中断。PRIMASK位：只允许NMI和hard fault异常，其他中断/异常都被屏蔽(当前CPU优先级=0)。 FAULTMASK位：只允许NMI，其他所有中断/异常都被屏蔽(当前CPU优先级=-1)。 在STM32固件库中(stm32f10x_nvic.c和stm32f10x_nvic.h) 定义了四个函数操作PRIMASK位和FAULTMASK位，改变CPU的当前优先级，从而达到控制所有中断的目的。 下面两个函数等效于关闭总中断： void NVIC_SETPRIMASK(void)； void NVIC_SETFAULTMASK(void)； 下面两个函数等效于开放总中断：void NVIC_RESETPRIMASK(void)； void NVIC_RESETFAULTMASK(void)； 上面两组函数要成对使用，但不能交叉使用。 例如： 第一种方法：NVIC_SETPRIMASK()；/关闭总中断 ，只允许NMI和hard fault异常NVIC_RESETPRIMASK()；/开放总中断 第二种方法： NVIC_SETFAULTMASK()；/关闭总中断 ，只允许NMINVIC_RESETFAULTMASK()；/开放总中断 常常使用： NVIC_SETPRIMASK(); / Disable Interrupts NVIC_RESETPRIMASK(); / Enable Interrupts可以用：#define CLI()_set_PRIMASK(1) /关闭总中断#define SEI()_set_PRIMASK(0) /打开总中断来实现开关总中断的功能。二、寄存器介绍：1、 在core_cm3.h中定义了：typedef struct _IO uint32_t ISER8; /*Offset:0x000(R/W)Interrupt Set Enable Register*/SETENA：中断0-239的使能寄存器；地址为：0xE000-E1000xE000-E11C；复位值：0 uint32_t RESERVED024;/未定义的寄存器 _IO uint32_t ICER8; /*Offset: 0x080 (R/W)Interrupt ClearEnable Register*/CLRENA：中断0-239的除能寄存器；地址为：0xE000-E1800xE000-E19C；复位值：0 uint32_t RSERVED124; /未定义的寄存器 _IO uint32_t ISPR8;/* Offset: 0x100 (R/W)Interrupt Set Pending Register*/SETPEND：中断0-239的悬起寄存器；地址为：0xE000-E2000xE000-E21C；复位值：0 uint32_t RESERVED224; /未定义的寄存器 _IO uint32_t ICPR8;/* Offset: 0x180 (R/W)Interrupt Clear Pending Register*/CLRPEND：中断0-239的解悬寄存器；地址为：0xE000-E2800xE000-E29C；复位值：0 uint32_t RESERVED324; /未定义的寄存器 _IO uint32_t IABR8; /*Offset: 0x200 (R/W)Interrupt Active bit Register*/ACTIVE：中断0-239的活动状态寄存器；地址为：0xE000-E3000xE000-E31C复位值：0 uint32_t RESERVED456; /未定义的寄存器_IO uint8_t IP240;/*Offset:0x300(R/W)Interrupt Priority Register(8Bit wide)*/中断优先级寄存器阵列(8位)：中断0-239的中断优先级；/地址为：0xE000-E4000xE000-E4EF；复位值：0uint32_t RESERVED5644; /未定义的寄存器 _IO uint32_t STIR; /* Offset: 0xE00 (R/W)Software Trigger Interrupt Register*/STIR：软件触发中断寄存器（如写入8则触发中断8的中断）；/地址为：0xE000-EF00；复位值：- NVIC_Type;#define SCS_BASE (0xE000E000) /*System Control Space Base Address */#define NVIC_BASE (SCS_BASE + 0x0100) /*NVIC Base Address */#define NVIC (NVIC_Type *)NVIC_BASE) /*NVIC configuration struct*/typedef struct _I uint32_t CPUID; /*Offset: 0x000 (R/ ) CPUID Base Register*/CPUID: -;地址为：0xE000-ED00；复位值：0x410fc230 _IO uint32_t ICSR; /*Offset: 0x004(R/W)Interrupt Control and State Register*/ICSR:中断控制及状态寄存器；地址为：0xE000-ED04；复位值：0 _IO uint32_t VTOR; /*Offset: 0x008 (R/W) Vector Table Offset Register*/VTOR:向量表偏移寄存器；地址为：0xE000-ED08；复位值：- _IO uint32_t AIRCR; /*Offset:0x00C(R/W)Application Interrupt and Reset Control Register*/ _IO uint32_t SCR; /*Offset: 0x010 (R/W) System Control Register*/ _IO uint32_t CCR; /*Offset: 0x014 (R/W) Configuration Control Register*/ _IO uint8_t SHP12; /*Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */_IO uint32_t SHCSR; /*Offset: 0x024 (R/W) System Handler Control and State Register*/ _IO uint32_t CFSR; /*Offset: 0x028 (R/W) Configurable Fault Status Register*/ _IO uint32_t HFSR; /*Offset: 0x02C (R/W) HardFault Status Register */ _IO uint32_t DFSR; /*Offset: 0x030 (R/W) Debug Fault Status Register*/ _IO uint32_t MMFAR; /*Offset: 0x034 (R/W) MemManage Fault Address Register*/ _IO uint32_t BFAR; /*Offset: 0x038 (R/W) BusFault Address Register*/ _IO uint32_t AFSR; /*Offset: 0x03C (R/W) Auxiliary Fault Status Register*/ _I uint32_t PFR2; /*Offset: 0x040 (R/ ) Processor Feature Register*/ _I uint32_t DFR; /*Offset: 0x048 (R/ ) Debug Feature Register*/ _I uint32_t ADR; /*Offset: 0x04C (R/ ) Auxiliary Feature Register*/ _I uint32_t MMFR4;/*Offset: 0x050 (R/ ) Memory Model Feature Register*/ _I uint32_t ISAR5; /*Offset: 0x060(R/ )Instruction Set Attributes Register*/ uint32_t RESERVED05; _IO uint32_t CPACR; /*Offset: 0x088 (R/W)Coprocessor Access Control Register*/ SCB_Type;#define SCS_BASE (0xE000E000) /*System Control Space Base Address */#define SCB_BASE (SCS_BASE + 0x0D00) /*System Control Block Base Address */#define SCB (SCB_Type *)SCB_BASE)/*SCB configuration struct*/三、初始化设置STM32中的设置的流程如下：选择的中断分组：NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); /选择中断分组1注意：优先级分组只能设置一次。定义的结构体变量：NVIC_InitTypeDef NVIC_InitStructure;选择要进行设置的模块：NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; /选择串口1中断进行抢占式中断优先级的设置：NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;/抢占式中断优先级设置为进行响应式中断优先级的设置：NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;/响应式中断优先级设置为3使能中断：NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;/使能中断根据上述设置进行初始化：NVIC_Init(&NVIC_InitStructure);注：NVIC_InitTypeDef的定义在中；的相关函数在中。NVIC_IRQChannel的取值列表：typedef enum IRQn/* Cortex-M3 Processor Exceptions Numbers */ NonMaskableInt_IRQn = -14, /*! 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*! 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*! 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*! 6 Cortex-M3 Usage Fault Interrupt */ SVCall_IRQn = -5, /*! 11 Cortex-M3 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*! 12 Cortex-M3 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*! 14 Cortex-M3 Pend SV Interrupt */ SysTick_IRQn = -1, /*! 15 Cortex-M3 System Tick Interrupt */* STM32 specific Interrupt Numbers */ WWDG_IRQn = 0, /*! Window WatchDog Interrupt */ PVD_IRQn = 1, /*! PVD through EXTI Line detection Interrupt */ TAMPER_IRQn = 2, /*! Tamper Interrupt */ RTC_IRQn = 3, /*! RTC global Interrupt */ FLASH_IRQn = 4, /*! FLASH global Interrupt */ RCC_IRQn = 5, /*! RCC global Interrupt */ EXTI0_IRQn = 6, /*! EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*! EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*! EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*! EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*! EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*! DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*! DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*! DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*! DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*! DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*! DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*! DMA1 Channel 7 global Interrupt */#ifdef STM32F10X_CL ADC1_2_IRQn = 18, /*! ADC1 and ADC2 global Interrupt */ CAN1_TX_IRQn = 19, /*! USB Device High Priority or CAN1 TX Interrupts */ CAN1_RX0_IRQn = 20, /*! USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*! CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*! CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*! External Line9:5 Interrupts */ TIM1_BRK_IRQn = 24, /*! TIM1 Break Interrupt */ TIM1_UP_IRQn = 25, /*! TIM1 Update Interrupt */ TIM1_TRG_COM_IRQn = 26, /*! TIM1 Trigger and Commutation Interrupt */ TIM1_CC_IRQn = 27, /*! TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*! TIM2 global Interrupt */ TIM3_IRQn = 29, /*! TIM3 global Interrupt */ TIM4_IRQn = 30, /*! TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*! I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*! I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*! I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*! I2C2 Error Interrupt */ SPI1_IRQn = 35, /*! SPI1 global Interrupt */ SPI2_IRQn = 36, /*! SPI2 global Interrupt */ USART1_IRQn = 37, /*! USART1 global Interrupt */ USART2_IRQn = 38, /*! USART2 global Interrupt */ USART3_IRQn = 39, /*! USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*! External Line15:10 Interrupts */ RTCAlarm_IRQn = 41, /*! RTC Alarm through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*! USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ TIM5_IRQn = 50, /*! TIM5 global Interrupt */ SPI3_IRQn = 51, /*! SPI3 global Interrupt */ UART4_IRQn = 52, /*! UART4 global Interrupt */ UART5_IRQn = 53, /*! UART5 global Interrupt */ TIM6_IRQn = 54, /*! TIM6 global Interrupt */ TIM7_IRQn = 55, /*! TIM7 global Interrupt */ DMA2_Channel1_IRQn = 56, /*! DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*! DMA2 Channel 2 global Interrupt */ DMA2_Channel3_IRQn = 58, /*! DMA2 Channel 3 global Interrupt */ DMA2_Channel4_IRQn = 59, /*! DMA2 Channel 4 global Interrupt */ DMA2_Channel5_IRQn = 60, /*! DMA2 Channel 5 global Interrupt */ ETH_IRQn = 61, /*! Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*! Ethernet Wakeup through EXTI line Interrupt */ CAN2_TX_IRQn = 63, /*! CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*! CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*! CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*! CAN2 SCE Interrupt */ OTG_FS_IRQn = 67 /*! USB OTG FS global Interrupt */#endif /* STM32F10X_CL */ IRQn_Type;使用库函数进行时钟系统初始化配置void NVIC_config()/配置中断NVIC_InitTypeDef NVIC_InitStructure;/NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);/选择中断分组1NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;/选择串口1中断NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;/抢占式中断优先级设置为NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;/响应式中断优先级设置为3NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;/使能中断NVIC_Init(&NVIC_InitStructure);四、相关库函数解析1、库中所涉及到的结构体typedef struct uint8_t NVIC_IRQChannel; /*! Specifies the IRQ channel to be enabled or disabled. This parameter can be a value of ref IRQn_Type (For the complete STM32 Devices IRQ Channels list, pleaserefer to stm32f10x.h file) */ uint8_t NVIC_IRQChannelPreemptionPriority; /*! Specifies the pre-emption priority for the IRQ channelspecified in NVIC_IRQChannel. This parameter can be a valuebetween 0 and 15 as described in the table ref NVIC_Priority_Table */ uint8_t NVIC_IRQChannelSubPriority; /*! Specifies the subpriority level for the IRQ channel specifiedin NVIC_IRQChannel. This parameter can be a valuebetween 0 and 15 as described in the table ref NVIC_Priority_Table */ FunctionalState NVIC_IRQChannelCmd; /*! Specifies whether the IRQ channel defined in NVIC_IRQChannelwill be enabled or disabled. This parameter can be set either to ENABLE or DISABLE */ NVIC_InitTypeDef;2、库函数解析在中：void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);对优先级分组进行配置void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);根据中断结构体的值初始化中断void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);设置向量表的位置和偏移void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 选择系统进入低功耗模式的条件void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);系统滴答时钟源的配置在中：uint32_t _get_BASEPRI(void);Return the Base Priority valuevoid _set_BASEPRI(uint3