奇数分频器(verilog).doc

奇数分频器/* Filename : odd_divider.v Author : Cardinal Company : Cardinal Revision : 2010/03/15 17:20 Description : Exercise of a odd divider 描述 : 这是一个奇数分频器 奇数分频法有多种实现方式，这里采用的是 错位相“或”法.这里实现的实现的是3分频 占空比是50%，类似可以实现任意的N次奇数 分频*/module ODD_DIVIDER( clk_in, rst_n, clk_out ); parameter width=2; input clk_in; input rst_n; output clk_out; reg width-1:0 cnt_posedge,cnt_negedge; reg clk_1toN_p,clk_1toN_n; always(posedge clk_in) /上升沿分频，占空比1:2 begin if(!rst_n) begin cnt_posedge=0; clk_1toN_p=0; end else if(cnt_posedge=2b10) cnt_posedge=0; else begin cnt_posedge=cnt_posedge+1; clk_1toN_p=clk_1toN_p; end end always(negedge clk_in) /下升沿分频，占空比1:2 begin if(!rst_n) begin cnt_negedge=0; clk_1toN_n=0; end else if(cnt_negedge=2b10) cnt_negedge=0; else begin cnt_negedge=cnt_posedge+1; clk_1toN_n=clk_1toN_n; end end assign clk_out=clk_1toN_n|clk_1toN_p; /错位相或 endmodule/* Filename : odd_divider_tp.v Author : Cardinal Company : Cardinal Revision : 2010/03/15 22:50 Description : the testbench of a odd divider*/timescale 1ns/1nsinclude odd_divider.vmodule odd_divider_tp; parameter width=2; parameter DELAY=100; reg clk_in; reg rst_n; wire clk_out; reg width-1:0 cnt_posedge; reg width-1:0 cnt_negedge; reg clk_1toN_p; reg clk_1toN_n; ODD_DIVIDER my_divider( .clk_in(clk_in), .clk_out(clk_out), .rst_n(rst_n) ); always #50 clk_in=clk_in; initial begin clk_in=0; rst_n=0; cnt_posedge=0; cnt_negedge=0; clk_1toN_p=0; clk_1toN_n=0; #DELAY rst_n=1; #(DELAY*20) $stop; end initial $monitor