硬件描述语言上机作业.doc

第一题：用Verilog语言的结构描述和行为描述分别设计下面的电路。 结构描述： 设计代码：module equal(y,a,b); input2:0 a,b; output y; wire w1,w2,w3; xor U1(w1,a0,b0)， U2(w2,a1,b1)， U3(w3,a2,b2); nor U4(y,w1,w2,w3);endmodule 仿真代码：timescale 1ns/1nsmodule equal_clk; reg5:0c; equal U1(.y(y),.a(c5,c4,c3),.b(c2,c1,c0); initial begin c=6b000_000; forever #2 c=c+1; end initial #500 $finish; initial $minitor($time,a=%b,b=%b,y=%b,c5,c4,c3,c2,c1,c0,y);endmodule 行为描述： 设计代码：module compare1(equal,a,b); input2:0 a,b; output equal; assign equal=(a=b)?1:0;endmodule 仿真代码：timescale 1ns/1nsmodule compare1_clk; reg5:0c; compare1 U(.equal(equal),.a(c5,c4,c3),.b(c2,c1,c0); initial begin c=6b000_000; forever #2 c=c+1; end initial #300 $finish; initial $monitor($time,a=%b,b=%b,equal=%b, c5,c4,c3,c2,c1,c0,equal);endmodule第二题：参数化电路设计1. 用行为描述方式实现下图所示的具有“one-hot”（独热）状态的环形计数器。要求使用参数化的模块。parameter SIZE =3;input clock, reset;output SIZE-1:0counter;说明：低电平同步复位，此时counter最低位为“1”，其余位均为“0”。2. 编写测试程序来验证该模块的正确性，要求测试对象是一个5位的独热状态环形计数器。 设计代码：module one_hot(counter,clock,reset); parameter SIZE =3; input clock, reset; output SIZE-1:0counter; reg SIZE-1:0counter; always (posedge clock) if(!reset) counter=8b0000_0001; else counter=counter0,counterSIZE-1:1;endmodule 仿真代码：timescale 1ns/1nsmodule one_hot_five; reg clk,rst; wire 4:0 cnt; one_hot #(5) U1(.counter(cnt),.clock(clk),.reset(rst); initial begin clk=0;rst=1; #2 rst=0;#5 rst=1; end always #5 clk=clk; initial #600 $finish; initial $monitor($time,counter=%b,clock=%b,reset=%b,cnt,clk,rst);endmodule第三题： 1用DFF实现二分频设计代码：module div2(clk_in,rst,clk_out); input clk_in,rst; output clk_out; reg clk_out; always (posedge clk_in or negedge rst) begin if(!rst) clk_out=0; else clk_out=clk_out; end endmodule 仿真代码：timescale 1ns/1nsmodule div2_tb; reg clock_in,reset; div2 U1(.clk_out(clock_out),.clk_in(clock_in),.rst(reset); initial begin clock_in=0; reset=1; #100 reset=0; #200 reset=1; #1000 reset=0; #500 reset=1; end always #50 clock_in=clock_in; initial $monitor($time,clk_in=%b,rst=%b,clk_out=%b,clock_in,reset,clock_out);endmodule2十进制计数器设计代码：module comp_10(count,clk,reset); output3:0count; input clk,reset; reg3:0count; always(posedge clk or negedge reset) if(reset) count=4b0000; else if(count=4b1001) count=4b0000; else count=count+1;endmodule仿真代码：timescale 1ns/1nsmodule comp_10_tb; reg clk,reset; wire3:0count; comp_10 U1(.count,.clk,.reset); always #10 clk=clk; initial begin clk=0;reset=0; #100 reset=1; #200 reset=0; #1000 reset=1; end initial $minitor($time,count=%b,clk=%b,reset=%b,count,clk,reset);endmodule第四题1五人投票A,B,C,D,E进行投票，多数服从少数，输出是F（也就是如果A,B,C,D,E中1的个数比0多，那么F输出为1，否则F为0），用与非门实现，输入数目没有限制。 设计代码:module vote(a,b,c,d,e,f); input a,b,c,d,e; output f; wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10; nand U1(w1,a,b,c); nand U2(w2,b,c,d); nand U3(w3,c,d,e); nand U4(w4,d,e,a); nand U5(w5,e,a,b); nand U6(w6,a,b,d); nand U7(w7,b,c,e); nand U8(w8,a,c,d); nand U9(w9,a,c,e); nand U10(w10,b,d,e); nand U11(f,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10);Endmodule 仿真代码：timescale 1ns/1nsmodule vote_tb; reg 4:0 z; vote U1(.f(F),.a(z4),.b(z3),.c(z2),.d(z1),.e(z0); initial begin z=5b0000; forever #2 z=z+1; end initial #1000 $finish; initial $monitor($time,f=%b,a=%b,b=%b,c=%b,d=%b,e=%b,F,z4,z3,z2,z1,z0);endmodule2四数比较 设a,b,c,d四个数，按从小到大的顺序重新排列并输出到ra,rb,rc,rd中。需在Verilog HDL描述中使用任务（task）。 设计代码：module rank(a,b,c,d,ra,rb,rc,rd); input 3:0 a,b,c,d; output 3:0 ra,rb,rc,rd; reg 3:0 ra,rb,rc,rd; reg 3:0 H1,H2,H3; reg 3:0 L1,L2,L3;always (a or b or c or d) begin rank(a,b,L1,H1); rank(c,d,L2,H2); rank(L1,L2,ra,H3); rank(H1,H2,L3,rd); rank(H3,L3,rb,rc); endtask rank; input 3:0 A,B; output 3:0 C,D; begin C=(AB)?A:B; D=(AB)?B:A; endendtaskendmodule 仿真代码：module rank_tb; reg 3:0 a,b,c,d;wire 3:0 ra,rb,rc,rd;initialbegina=$random%16;b=$random%16;c=$random%16;d=$random%16;repeat(8)#100a=$random%16;b=$random%16;c=$random%16;d=$random%16;endrank U1(.ra,.rb,.rc,.rd,.a,.b,.c,.d);initial $monitor($time,a=%d,b=%d,c=%d,d=%d,ra=%d,rb=%d,rc=%d,rd=%d,a,b,c,d,ra,rb,rc,rd);endmodule第五题1卖报机设计一个接受1，2，5分钱的卖报机，每份报纸5分钱，并考虑找零。 设计代码：module auto_newsy(coin,return,news,clk,rst); input 2:0coin; input clk,rst; output 2:0return; output news; reg 2:0state,next,return; reg news; parameter ST00=3B000,ST01=3B001,ST02=3B010,ST03=3B011,ST04=3B100; always (state or coin) case(state) ST00:case(coin) 3b000:begin next=ST00; news=3b000; return=3b000; end 3b001:begin next=ST01; news=0; return=3b000; end 3b010:begin next=ST02; news=0; return=3b000; end 3b101:begin next=ST00; news=1; return=3b000; end endcase ST01:case(coin) 3b000:begin next=ST01; news=0; return=3b000; end 3b001:begin next=ST02; news=0; return=3b000; end 3b010:begin next=ST03; news=0; return=3b000; end 3b101:begin next=ST00; news=1; return=3b001; end endcase ST02:case(coin) 3b000:begin next=ST02; news=0; return=3b000; end 3b001:begin next=ST03; news=0; return=3b000; end 3b010:begin next=ST04; news=0; return=3b000; end 3b101:begin next=ST00; news=1; return=3b010; end endcase ST03:case(coin) 3b000:begin next=ST03; news=0; return=3b000; end 3b001:begin next=ST04; news=0; return=3b000; end 3b010:begin next=ST00; news=1; return=3b000; end 3b101:begin next=ST00; news=1; return=3b011; end endcase ST04:case(coin) 3b000:begin next=ST04; news=0; return=3b000; end 3b001:begin next=ST00; news=1; return=3b000; end 3b010:begin next=ST00; news=1; return=3b001; end 3b101:begin next=ST04; news=1; return=3b100; end endcaseendcasealways (posedge clk or negedge clk) if(!rst) state=ST00; else state=next;endmodule仿真代码：timescale 1ns/1nsmodule auto_newsy_tb; reg clk,rst; wire 2:0return; wire news; reg 2:0coin; auto_newsy U1(.coin(coin),.return(return),.news(news),.clk(clk),.rst(rst); initial begin clk=0;rst=1; #2 rst=0;#5 rst=1; end initial begin repeat(6) begin #10 coin=3b000; #10 coin=3b001;#10 coin=3b001;#10 coin=3b001;#10 coin=3b001;#10 coin=3b001; #10 coin=3b010;#10 coin=3b010;#10 coin=3b010;#10 coin=3b010;#10 coin=3b010; #10 coin=3b101;#10 coin=3b101;#10 coin=3b101;#10 coin=3b101;#10 coin=3b101; end end always #5 clk=clk; initial #3000 $finish; initial $monitor($time,coin=%b,return=%b,news=%b,clk=%b,rst=%b,coin,return,news,clk,rst);endmodule2状态机利用状态机设计一个“10011”序列检测器，该检测器具有如下行为：在每一个时钟下降沿检查输入数据，当输入数据序列为“10011”时，输出asm被置为1；其余情况asm为0。要求：画出fsm（有限状态机） 设计代码：module status_10011(a,clk,rst,asm); input a,clk,rst; output asm; parameter 2:0 s0 =3b000, s1 =3b001, s2 =3b010,