四位全加器的VHDL设计.ppt

四位全加器的VHDL设计 一位全加器真值表 一位全加器的逻辑表达式 S A B CinCo AB BCin ACin其中A B为要相加的数 Cin为进位输入 S为和 Co是进位输出 Libraryieee Useieee std logic 1164 all Useieee std logic unsigned all EntityfulladderIsPort Ci a b INstd logic s Co OUTstd logic Endfulladder Architecturem1OffulladderIsSignaltmp std logic vector 1downto0 Begintmp 0 一位全加器的数据流 逻辑 描述 Libraryieee Useieee std logic 1164 all Useieee std logic unsigned all EntityfulladderisPort A B CI instd logic S CO outstd logic Endfulladder ArchitecturedataflowoffulladderisBeginS CIxorAxorB CO AandB or CIandA or CIandB Enddataflow 一位全加器的行为描述 Libraryieee Useieee std logic 1164 all Useieee std logic unsigned all EntityfulladderisPort a b cin Inbit sum cout Outbit Endfulladder ArchitecturebehaveOffulladderIsBeginProcess a b cin BeginIf aOrbOrcin 0 Thensum 0 cout 0 Elsif aANDbANDcin 1 Thensum 1 cout 1 Elsif aXORbXORcin 0 Thensum 0 cout 1 Elsesum 1 cout 0 EndIf EndProcess Endbehave 4位全加器的设计 先设计4个1位的全加器 然后将低位的进位输出与高位的进位输入相连 将要进行加法运算的两个4位数的每一位分别作为每一个1位全加器的输入 进行加法运算 所有的1位全加器的输出组成一个4位数 即输入的两个4位数之和 最高位的全加器产生的进位输出即两个4位数求和的进位输出 如图 Libraryieee Useieee std logic 1164 all Useieee std logic unsigned all Entityadder4IsPort Cin INstd logic x y INstd logic vector 3downto0 sum OUTstd logic vector 3downto0 Cout OUTstd logic Endadder4 ArchitectureaxOfadder4IsSignalc std logic vector 0to4 ComponentfulladderPort Ci a b INstd logic s Co OUTstd logic Endcomponent Beginc 0 c 0 a x 0 b y 0 s sum 0 Co c 1 U2 fulladderPortMap c 1 x 1 y 1 sum 1 c 2 U3 fulladderPortMap c 2 x 2 y 2 sum 2 c 3 U4 fulladderPortMap c 3 x 3 y 3 sum 3 c 4 Cout c 4 Endax libraryieee useieee std logic 1164 all useieee std logic unsigned all entityadder4bitisport cin instd logic a b instd logic vector 3downto0 s outstd logic vector 3downto0 cout outstd logic endadder4bit architecturebehofad