现代计算机组成原理.doc

数字系统组原理和设计技术课程报告类16位处理器姓 名：蒋旭源班 级：11电子A学 号：1115105024任课教师：邱 应 强一、前言本来我们这组是设计一个16位并行的CPU,由于书中及网络所提供的资料所使用用的版本与我们所使用的Quartus II 7.2版本有区别,所以我们组才用一个8位串行cpu来代替16位并行cpu的功能.虽然在运算功能上没有本质上的区别,但在运行速度上,时间上有着比较明显的差距.可惜资料不足,使成品完成度不高二、设计目的理解16位cpu的功能及组成原理,深入学习计算机各类典型指令的执行流程,掌握部件单元电路设计的相关技术,调试方法三、实验设备及工具硬件：实验平台、PC 机。软件：Quartus II 7.2四、设计方案的比较我们在这个设计上有3种设计方案:根据书上第六章所给的部份程序:由于大部分逻辑状态是直接利在top.vhd中及在顶层例化中实现,但由于在top.vhd文件是用于统合及测试所有部件及指令,但由top.vhd文件中出现了一句在现有的元件库中,没有的语句,需要另外另编写,可是在这是内部程文件,所以没法在外部编写,但在其他版本如9.0等版本郤增加了该元件库.在该基础上利用顶层来设置逻辑定义,使书中逻辑字句不用通过top.vhd来实现测试功能,并可直接通过加载到测试板中直接测试,但由于不是直接定义,所以大部分器件因应不同的需要加入与 或 非等门,使因为利用2进制代码的替换所引起缺失利用8位cpu的高低位来实16位的指令的功能,由于8位cpu在数据处理上比16位困难,因为要在原在的分位上加入3位判断位,以便于实现16位的处理功能在以上3种方案中,由于第一种方案在设计软体上出现明显的缺陷,在由老师所是供的意见下如把程序中的逻辑替换成2进制代码时会出现逻辑缺失,在第二种方案在后期才被发现,而且已经被别的同学所做出来,而我们组在讨论初期,只有方案1方案3两个,而我们在当时没有想出方案2,所以在方案的选取时,我们就决定了方案3为我们的设计方向并开始设计.五、设计原理利用8位与16位想同的部件但输入输出端口不同而的部件程序来实现,并用原理图的设计方法来实现功能或指令,总体分为:1)时钟发生器 2)指令寄存器 3)累加器 4) CPU算术逻辑运算单元 5)数据控制器 6)状态控制器 7)程序计数器 8)地址多路器 而在设计上我们采用局部原理图化及顶层例化,在主要数据运算利用中我们使用了原理图做了一个类16位的cpu运算总体,如下图所示总体原来如下:在运行时,由外部时钟决定了运算部总体的运作,当CLK1为所对应的state_type中S0S7,为指令寄存器,ALU及状态机等时钟信号如:当state_type中S1为高电平时,ALU中的CLK就同时为高电平,我们用这种方式来决定部件的运行的先后次序,在,然后就会把ALU所运行完或结束的程序计数,并把结果发送给累加器作记录,并通过状态控制器去制判断是未要使用ROM中的预设中调出需用的其它微程序及指令,部件程序:分频时钟LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity freqdivide isport(clk: in std_logic;-reset: in std_logic;clk1:out std_logic;alu_clk: out std_logic;fetch: out std_logic);end freqdivide;architecture win of freqdivide isbegin clk1state:=S1;when S1 =alu_clkalu_clkfetchstate:=S5;when S5 =state:=S6;when S6 =state:=S7;when S7 =fetchstate:=S1;when others =state:=S0;end case;else null;end if;end process main;end win;状态机控制器LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity machinectl isport(clk:in std_logic;fetch: in std_logic;reset: in std_logic;ena: out std_logic);end machinectl;architecture win of machinectl isbegin process(clk,reset,fetch)beginif(clkevent and clk=0)thenif(reset=1)thenena=0;elsif(fetch=1)thenena=1;else null;end if;else null;end if;end process;end win;指令寄存器LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity instrreg isport(clk: in std_logic;reset: in std_logic;ena: in std_logic;data: in std_logic_vector(7 downto 0);opc_iraddrs1:out std_logic_vector(2 downto 0);opc_iraddrs2:out std_logic_vector(12 downto 0);end instrreg;architecture win of instrreg isbegin main:process(clk,reset)type state_type is (S0,S1,S2);variable state:state_type;beginif(clkevent and clk=1)thenif(reset=1)thenopc_iraddrs1=111;opc_iraddrs2opc_iraddrs1=data(7 downto 5);opc_iraddrs2(12 downto 8)opc_iraddrs2(7 downto 0)opc_iraddrs1=ZZZ;opc_iraddrs2=ZZZZZZZZZZZZZ;state:=S2;end case;else state:=S0;end if;else null;end if;end process main;end win;累加器LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity accumulator isport(clk: in std_logic;reset: in std_logic;ena: in std_logic;data: in std_logic_vector(7 downto 0);accum:out std_logic_vector(7 downto 0);end accumulator;architecture win of accumulator isbegin main:process(clk,reset,ena)beginif(clkevent and clk=1)thenif(reset=1)thenaccum=00000000;elsif(ena=1)thenaccum alu_out alu_out alu_out alu_out alu_out alu_out alu_out alu_out alu_out=ZZZZZZZZ;end case;else null;end if;end process main;zero=not (accum(0) or accum(1) or accum(2) or accum(3) or accum(4) or accum(5) or accum(6) or accum(7);end win;程序计数器LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.std_logic_unsigned.ALL;USE IEEE.std_logic_arith.ALL;entity counter isport(ir_addr:in std_logic_vector(12 downto 0);load: in std_logic;clock: in std_logic;rst: in std_logic;pc_addr:out std_logic_vector(12 downto 0);end counter;architecture win of counter issignal pc_addr_reg:std_logic_vector(12 downto 0);-signal pc_addr_rst:std_logic_vector(12 downto 0);begin process(rst,load,clock,ir_addr)-variable pc_addr_reg:std_logic_vector(12 downto 0);beginif(rst=0)thenif(clockevent and clock=1)thenif(load=0)thenpc_addr_reg=pc_addr_reg+1;else pc_addr_reg=ir_addr;end if;else null;end if;elsepc_addr_reg=0000000000000;end if;end process;pc_addr=pc_addr_reg;end win; 地址多路器LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity addrchos isport(fetch:in std_logic;pc_addr: in std_logic_vector(12 downto 0);ir_addr: in std_logic_vector(12 downto 0);addr: out std_logic_vector(12 downto 0);end addrchos;architecture win of addrchos isbegin process(pc_addr,ir_addr,fetch)beginif(fetch=1)thenaddr=pc_addr;else addr=ir_addr;end if;end process;end win;数据控制器LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity datactl isport(data_in: in std_logic_vector(7 downto 0);data_ena: in std_logic;data: out std_logic_vector(7 downto 0);end datactl;architecture win of datactl isbegin process(data_in,data_ena)beginif(data_ena=1)thendata=data_in;else data=ZZZZZZZZ;end if;end process;end win;状态机(控制器)LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity statectl isport(clk1: in std_logic;-the clock of cpuzero: in std_logic;-data of acc is zeroena: in std_logic;-enable portopcode: in std_logic_vector(2 downto 0);-operation codeinc_pc:out std_logic;-increase pc pointload_acc: out std_logic;-acc output enableload_pc: out std_logic;-pc point loadrd:out std_logic;-read from ROMwr:out std_logic;-write to RAMload_ir:out std_logic;-load target addressdatactl_ena:out std_logic;-data out enablehalt:out std_logic);-halt codeend statectl;architecture win of statectl isbegin main:process(clk1,zero,ena,opcode)type state_type is (clk_0,clk_1,clk_2,clk_3,clk_4,clk_5,clk_6,clk_7);-define eight state represent for eight clocksvariable state:state_type;-define eight codes using constant standard logicconstant HLT:std_logic_vector:= 000;constant SKZ:std_logic_vector:= 001;constant ADD:std_logic_vector:= 010;constant ANDD:std_logic_vector:=011;constant XORR:std_logic_vector:=100;constant LDA:std_logic_vector:= 101;constant STO:std_logic_vector:= 110;constant JMP:std_logic_vector:= 111;beginif(clk1event and clk1=0)then-the negative edge of clockif(ena=0)then-state loop enablestate:=clk_0;inc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt-the zreoth clockinc_pc=0;load_acc=0;load_pc=0;rd=1;-read from ROMwr=0;load_ir=0;datactl_ena=0;halt-the first clockinc_pc=1;load_acc=0;load_pc=0;rd=1;-pc increase ,read from ROMwr=0;load_ir=1;datactl_ena=0;halt-the second clockinc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt-the third clockif(opcode=HLT)theninc_pc=1;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt=1;else inc_pc=1;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt-the forth clockif(opcode=JMP)theninc_pc=0;load_acc=0;load_pc=1;rd=0;wr=0;load_ir=0;datactl_ena=0;halt=0;elsif(opcode=ADD or opcode=ANDD or opcode=XORR or opcode=LDA)theninc_pc=0;load_acc=0;load_pc=0;rd=1;wr=0;load_ir=0;datactl_ena=0;halt=0;elsif(opcode=STO)theninc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=1;halt=0;else inc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt-the fifth clockif(opcode=ADD or opcode=ANDD or opcode=XORR or opcode=LDA)theninc_pc=0;load_acc=1;load_pc=0;rd=1;wr=0;load_ir=0;datactl_ena=0;halt=0;elsif(opcode=SKZ and zero=1)theninc_pc=1;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt=0;elsif(opcode=JMP)theninc_pc=1;load_acc=0;load_pc=1;rd=0;wr=0;load_ir=0;datactl_ena=0;halt=0;elsif(opcode=STO)theninc_pc=0;load_acc=0;load_pc=0;rd=0;wr=1;load_ir=0;datactl_ena=1;halt=0;else inc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt-the sixth clockif(opcode=STO)theninc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=1;halt=0;-output the dataelsif(opcode=ADD or opcode=ANDD or opcode=XORR or opcode=LDA)theninc_pc=0;load_acc=0;load_pc=0;rd=1;wr=0;load_ir=0;datactl_ena=0;halt=0;else inc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt-the seventh clockif(opcode=SKZ and zero=1)theninc_pc=1;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt=0;else inc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt-for other state(s)inc_pc=0;load_acc=0;load_pc=0;rd=0;wr=0;load_ir=0;datactl_ena=0;halt=0;state:=clk_0;end case;end if;else null;end if;end process main;end win;RAMLIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity ram isport(DATA: inout std_logic_vector(7 downto 0);ADDR: in integer range 0 to 255;ENA: in std_logic;RD: in std_logic;WR: in std_logic);end ram;architecture zhw of ram isbegin process(RD,ENA,WR,ADDR,DATA)type ram_array is array(0 to 255) of std_logic_vector(7 downto 0);variable mem:ram_array;beginif(ENA=1)thenif(RD=1 and WR=0)thenDATA=mem(ADDR);elsif(WR=1 and RD=0)thenmem(ADDR):=DATA;else DATAZ);end if;elseDATAZ);end if;end process;end zhw;ROMLIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity rom isport(DATA: out std_logic_vector(7 downto 0);ADDR: in integer range 0 to 8191;ENA: in std_logic;RD: in std_logic;ROMDATA:out std_logic_vector(7 downto 0);end rom;architecture zhou of rom isbegin process(ADDR,ENA,RD)type rom_array is array(0 to 8191) of std_logic_vector(7 downto 0);variable mem:rom_array:=(00000000),-HALT(00100110),-1(11010000),-STO(00000000),-3(00000000),-HALT(00000000),-5(11100000),-JMP 0x0008(00001000),-7(00000000),-HALT(00100110),-9(11100000),-JMP 0x0008(00001000),-11(11000000),(00000000),-13(00000000),(00000000),-15(10100011),(11000100),-17(11100101),(11100110),-19(00000000),(00000000),-21(11000000),(00000000),-23(00000000),(00000000),-25(10100011),(11000100),-27(11100101),(11100110),-29(00000000),(00000000),-31(11000000),(00000000),-33(00000000),(00000000),-35(00000001),(11000100),-37(11111111),(00000010),-39others=(11111111);beginROMDATA=mem(ADDR);if(ENA=1 and RD=1)thenDATA=mem(ADDR);elseDATAZ);end if;end process;end zhou; 地址译码器LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;entity addr_decode isport(ADDR: in std_logic_vector(12 downto 0);RAM_SEL: out std_logic;ROM_SEL: out std_logic);end addr_decode;architecture win of addr_decode isbegin process(ADDR)begincase ADDR(12 downto 11) iswhen 11 =RAM_SEL=1;ROM_SELRAM_SEL=0;ROM_SELRAM_SEL=0;ROM_SELRAM_SEL=0;ROM_SELRAM_SEL=0;ROM_SEL=0;end case;end process;end win;运算总体的例化LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.std_logic_unsigned.ALL;USE IEEE.std_logic_arith.ALL;entity main isport(CLK:in std_logic;RST: in std_logic;ADDR:out std_logic_vector(12 downto 0);RD:out std_logic;WR:out std_logic;HALT:out std_logic;DATA:inout std_logic_vector(7 downto 0);end main;architecture behav of main iscomponent accumulatorport(clk: in std_logic;reset: in std_logic;ena: in std_logic;data: in std_logic_vector(7 downto 0);accum:out std_logic_vector(7 downto 0);end component;component addrchosport(fetch:in std_logic;pc_addr: in std_logic_vector(12 downto 0);ir_addr: in std_logic_vector(12 downto 0);addr: out std_logic_vector(12 downto 0);end component;component ALUport(alu_clk: in std_logic;opcode: in std_logic_vector(2 downto 0);accum: in std_logic_vector(7 downto 0);data: in std_logic_vector(7 downto 0);alu_out:out std_logic_vector(7 downto 0);zero: out std_logic);end component;component datactlport(data_in: in std_logic_vector(7 downto 0);data_ena: in std_logic;data: out std_logic_vector(7 downto 0);end component;component freqdivide port(clk: in std_logic;clk1:out std_logic;alu_clk: out std_logic;fetch: out std_logic);end component;component instrregport(clk: in std_logic;reset: in std_logic;ena: in std_logic;data: in std_logic_vector(7 downto 0);opc_iraddrs1:out std_logic_vector(2 downto 0);opc_iraddrs2:out std_logic_vector(12 downto 0);end component;component machinectlport(clk:in std_logic;fetch: in std_logic;reset: in std_logic;ena: out std_logic);end component;component statectlport(clk1: in std_logic;-the clock of cpuzero: in std_logic;-data of acc is zeroena: in std_logic;-enable portopcode: in std_logic_vector(2 downto 0);-operation codeinc_pc:out std_logic;-increase pc pointload_acc: out std_logic;-acc output enableload_pc: out std_logic;-pc point loadrd:out std_logic;-read from ROMwr:out std_logic;-write to RAMload_ir:out std_logic;-load target addressdatactl_ena:out std_logic;-data out enablehalt:out std_logic);-halt codeend component;component counterport(ir_addr:in std_logic_vector(12 downto 0);load: in std_logic;clock: in std_logic;rst: in std_logic;pc_addr:out std_logic_vector(12 downto 0);end component;signal carry_out1:std_logic;-clk1signal carry_out2:std_logic;-load_accsignal carry_out3:std_logic_vector(7 downto 0);-data(accun)signal carry_out4:std_logic_vector(7 downto 0);-accumsignal carry_out5:std_logic;-fetchsignal carry_out6:std_logic_vector(12 downto 0);-pc_addrsignal carry_out7:std_logic_vector(12 downto 0);-ir_addrsign