VHDL重的testbeach写法.docx

弄了好长时间vhdl，一直对testbench很迷惑。前几天静下心来好好看了下资料，终于会写简单的testbench了。六进制计数器的代码c-sharpview plaincopy1. libraryieee;2. useieee.std_logic_1164.all;3. useieee.std_logic_arith.all;4. -useieee.std_logic_unsigned.all;5. 6. entitycnt6is7. port8. (clr,en,clk:instd_logic;9. q:outstd_logic_vector(2downto0)10. );11. endentity;12. 13. architecturertlofcnt6is14. signaltmp:std_logic_vector(2downto0);15. begin16. process(clk)17. -variableq6:integer;18. begin19. if(clkeventandclk=1)then20. if(clr=0)then21. tmp=000;22. elsif(en=1)then23. if(tmp=101)then24. tmp=000;25. else26. tmp=unsigned(tmp)+1;27. endif;28. endif;29. endif;30. q=tmp;31. -qa=q(0);32. -qb=q(1);33. -qcclk,en=en,clr=clr,q=q25. );26. clk_gen:process27. begin28. waitforclk_period/2;29. clk=1;30. waitforclk_period/2;31. clk=0;32. endprocess;33. 34. clr_gen:process35. begin36. clr=0;37. waitfor30ns;38. clr=1;39. wait;40. endprocess;41. 42. en_gen:process43. begin44. en=0;45. waitfor50ns;46. en=1;47. wait;48. endprocess;49. endrtl;其实testbench也有自己固定的一套格式，总结如下：c-sharpview plaincopy1. -测试平台文件(testbench)的基本结构2. libraryieee;3. useieee.std_logic_1164.all;4. 5. entitytest_benchis-测试平台文件的空实体（不需要端口定义)6. 7. endtest_bench;8. 9. architecturetb_behavioroftest_benchis10. componententity_under_test-被测试元件的声明11. port(12. list-of-ports-theri-types-and-modes13. );14. endcomponent;15. 16. begin17. instantiation:entity_under_testportmap18. (19. port-associations20. );21. 22. process()-产生时钟信号23. 24. endprocess;25. 26. process()-产生激励源27. 28. endprocess;29. endtb_behavior;30. 31. -32. -简单计数程序源码33. libraryieee;34. useieee.std_logic_1164.all;35. useieee.std_logic_unsigned.all;36. useieee.std_logic_unsigned.all;37. 38. entitysim_counteris39. port(40. clk:instd_logic;41. reset:instd_logic;42. count:outstd_logic_vector(3downto0)43. );44. endentity;45. 46. architecturebehavioralofsim_counteris47. 48. signaltemp:std_logic_vector(3downto0);49. 50. begin51. process(clk,reset)52. begin53. ifreset=1then54. temp=0000;55. elsifclkeventandclk=1then56. temp=temp+1;57. endif;58. endprocess;59. countclk,reset=reset,counter=counter92. );93. clk_gen:process94. begin95. clk=1;96. waitforclk_period/2;97. clk=0;98. waitforclk_period/2;99. endprocess;100. 101. tb:process-激励信号102. begin103. waitfor20ns;104. reset=1;105. waitfor20ns;106. reset=0;107. waitfor200ns;108. wait;-willwaitforever;109. endprocess;110. end;111. 112. 113. -激励信号的产生方式114. -1.以一定的离散时间间隔产生激励信号的波形115. -2.基于实体的状态产生激励信号，也就是说基于实体的输出响应产生激励信号116. 117. -两种常用的复位信号118. -1.周期性的激励信号，如时钟119. -2.时序变化的激励型号，如复位120. 121. -eg.产生不对称时钟信号122. w_clkstart-start test bench template write这里需要注意的是要在仿真选项里选择一个仿真工具，然后才会生成testbench自动生成的testbench模板格式如下：c-sharpview plaincopy1. -Copyright(C)1991-2008AlteraCorporation2. -YouruseofAlteraCorporationsdesigntools,logicfunctions3. -andothersoftwareandtools,anditsAMPPpartnerlogic4. -functions,andanyoutputfilesfromanyoftheforegoing5. -(includingdeviceprogrammingorsimulationfiles),andany6. -associateddocumentationorinformationareexpresslysubject7. -tothetermsandconditionsoftheAlteraProgramLicense8. -SubscriptionAgreement,AlteraMegaCoreFunctionLicense9. -Agreement,orotherapplicablelicenseagreement,including,10. -withoutlimitation,thatyouruseisforthesolepurposeof11. -programminglogicdevicesmanufacturedbyAlteraandsoldby12. -Alteraoritsauthorizeddistributors.Pleaserefertothe13. -applicableagreementforfurtherdetails.14. 15. -*16. -ThisfilecontainsaVhdltestbenchtemplatethatisfreelyeditableto17. -suitusersneeds.Commentsareprovidedineachsectiontohelptheuser18. -filloutnecessarydetails.19. -*20. -Generatedon03/13/201120:05:0421. 22. -VhdlTestBenchtemplatefordesign:cnt623. -24. -Simulationtool:ModelSim(VHDL)25. -26. 27. LIBRARYieee;28. USEieee.std_logic_1164.all;29. 30. ENTITYcnt6_vhd_tstIS31. ENDcnt6_vhd_tst;32. ARCHITECTUREcnt6_archOFcnt6_vhd_tstIS33. -constants34. -signals35. SIGNALclk:STD_LOGIC;36. SIGNALclr:STD_LOGIC;37. SIGNALen:STD_LOGIC;38. SIGNALq:STD_LOGIC_VECTOR(2DOWNTO0);39. COMPONENTcnt640. PORT(41. clk:INSTD_LOGIC;42. clr:INSTD_LOGIC;43. en:INSTD_LOGIC;44. q:OUTSTD_LOGIC_VECTOR(2DOWNTO0)45. );46. ENDCOMPONENT;47. BEGIN48. i1:cnt649. PORTMAP(50. -listconnectionsbetweenmasterportsandsignals51. clk=clk,52. clr=clr,53. en=en,54. q=q55. );56. init:PROCESS57. -variabledeclarations58. BEGIN59. -codethatex