基于FPGA的psk调制.doc

西 南 交 通 大 学信 息 科 学 与 技 术 学 院通 信 工 程 专 业 工 程 实 习 报 告（psk调制解调器的FPGA实现）课题设计报告年 级: 2010 学 号: 20100147 姓 名: 刘 妍 专 业: 通信工程 二零一三年七月一、 （psk调制解调器的FPGA实现）总体设计基本原理PSK调制原理相移键控(PSK)：一种用载波相位表示输入信号信息的调制技术。移相键控分为绝对移相和相对移相两种。以未调载波的相位作为基准的相位调制叫作绝对移相。以二进制调相为例，取码元为“1”时，调制后载波与未调载波同相；取码元为“0”时，调制后载波与未调载波反相；“1”和“0”时调制后载波相位差180度。PSK 调制原理图：PSK 解调原理2PSK信号的解调只能用相干解调一种形式。解调原理框图及波形如图所示:二、详细设计顶层模块 module bpsk(clk,reset_n,clk_DA,blank_DA_n,sync_DA_n,dataout,dm_out);input clk ;input reset_n ;output clk_DA ; output blank_DA_n; output sync_DA_n ; output 7 : 0 dataout ;output 7 : 0 dm_out;wire 6 : 0 address ;wire dataoutm ;wire clk1 ;wire 7 : 0 dataout;counter COUNTER( .clk ( clk ),.reset_n (reset_n),.count (count),.clk1 ( clk1 ); PN_Seq PN_SEQ( .clk1 ( clk1 ),.reset_n ( reset_n ),.dataoutm ( dataoutm );Controller CONTROLLER(.clk ( clk ),.reset_n ( reset_n ),.dataoutm ( dataoutm),.address ( address ),.clk_DA ( clk_DA ),.blank_DA_n( blank_DA_n ),.sync_DA_n ( sync_DA_n );LookUpTable LOOKUPTABLE (.clk ( clk ),.reset_n ( reset_n ),.address ( address ),.dataout ( dataout ); depsk depsk( .clk (clk),.reset_n (reset_n),.data (dataout),.dataout (dm_out) );endmoduleendmodule分频模块module counter(clk,reset_n,count,clk1); input clk,reset_n; output clk1; output6:0 count; reg clk1; reg6:0 count; parameter N = 128; always (posedge clk or negedge reset_n ) if(! reset_n) begin count = 1b0; clk1 = 1b0; end else if ( count 63) begin count = count + 1b1; end else begin count = 1b0; clk1 = clk1; endendmoduleM 序列产生模块module PN_Seq(clk1,reset_n,dataoutm); input clk1; input reset_n;output dataoutm;reg 7 : 1 c;always ( posedge clk1 or negedge reset_n )begin if(!reset_n) c=7b1000000; else begin c2=c1; c3=c2; c4=c3; c5=c4; c6=c5; c7=c6; c1=c2c3c4c7;endendassign dataoutm = c7;endmodule控制器模块 module Controller(clk,reset_n, dataoutm, address,clk_DA,blank_DA_n,sync_DA_n);input clk ;input reset_n ;input dataoutm ;output 6 : 0 address ;output clk_DA ; output sync_DA_n ; output blank_DA_n ; reg 6 : 0 address_data1;reg 6 : 0 address_data2;reg 6 : 0 address_data;/ always (dataoutm)/ begin/ case(dataoutm)/ 1b0: begin / address_data=address_data2;/ end/ 1b1: begin/ address_data=address_data1;/ end/ default:begin/ address_data=5bzzzzz;/end/ endcase/ endalways ( posedge clk or negedge reset_n )begin if(!reset_n) / begin address_data1=7b011_1111;/000_0000;/定义初值相位 address_data2=7b000_0000;/111_0011;/定义初值0 end else / begin address_data1=address_data1+7b000_0001;/地址依次加一 address_data2=address_data2+7b000_0001; endendalways ( posedge clk or negedge reset_n )begin if(!reset_n) address_data=7b000_0000;/赋初值 else if(!dataoutm) address_data=address_data2;/如果m序列输出为0，则为address_data2值 else if(dataoutm) address_data=address_data1; else;end assign address = address_data;assign clk_DA = clk;assign blank_DA_n = 1b1;assign sync_DA_n = 1b1; endmodule查找表模块 module LookUpTable(clk,reset_n,address,dataout,);input clk;input reset_n;input 6 : 0 address;output 7 : 0 dataout;reg 7 : 0 LUT 0 : 127 ;always ( posedge clk or negedge reset_n )beginLUT 34 = 115;LUT 35 = 109;LUT 36 = 103;LUT 37 = 97;LUT 38 = 91;LUT 39 = 85;LUT 40 = 79;LUT 41 = 73;LUT 42 = 68;LUT 43 = 62;LUT 44 = 57;LUT 45 = 52;LUT 46 = 47;LUT 47 = 42;LUT 48 = 38;LUT 49 = 33;LUT 50 = 29;LUT 51 = 25;LUT 52 = 22;LUT 53 = 19;LUT 54 = 15;LUT 55 = 13;LUT 56 = 10;LUT 57 = 8;LUT 58 = 6;LUT 59 = 4;LUT 60 = 3;LUT 61 = 2;LUT 62 = 1;LUT 63 = 1;LUT 64 = 0;LUT 65 = 1;LUT 66 = 1;LUT 67 = 2;LUT 68 = 3;LUT 69 = 4;LUT 70 = 6;LUT 71 = 8;if( !reset_n )beginLUT 0 = 255;LUT 1 = 254;LUT 2 = 253;LUT 3 = 252;LUT 4 = 251;LUT 5 = 250;LUT 6 = 248;LUT 7 = 246;LUT 8 = 244;LUT 9 = 241;LUT 10 = 239;LUT 11 = 235;LUT 12 = 232;LUT 13 = 229;LUT 14 = 225;LUT 15 = 221;LUT 16 = 216;LUT 17 = 212;LUT 18 = 207;LUT 19 = 202;LUT 20 = 197;LUT 21 = 192;LUT 22 = 186;LUT 23 = 181;LUT 24 = 175;LUT 25 = 169;LUT 26 = 163;LUT 27 = 157;LUT 28 = 151;LUT 29 = 145;LUT 30 = 139;LUT 31 = 133;LUT 32 = 127;LUT 33 = 121;LUT 122 = 248;LUT 123 = 250;LUT 124 = 251;LUT 125 = 252;LUT 126 = 253;LUT 127 = 255;endendassign dataout = LUT address ;endmoduleLUT 72 = 10;LUT 73 = 13;LUT 74 = 15;LUT 75 = 19;LUT 76 = 22;LUT 77 = 25;LUT 78 = 29;LUT 79 = 33;LUT 84 = 57;LUT 85 = 62;LUT 86 = 68;LUT 87 = 73;LUT 88 = 79;LUT 89 = 85;LUT 90 = 91;LUT 91 = 97;LUT 92 = 103;LUT 93 = 109;LUT 94 = 115;LUT 95 = 121;LUT 96 = 127;LUT 97 = 133;LUT 98 = 139;LUT 99 = 145;LUT 100 = 151;LUT 101 = 157;LUT 102 = 163;LUT 103 = 169;LUT 104 = 175;LUT 105 = 181;LUT 106 = 186;LUT 107 = 192;LUT 108 = 197;LUT 109 = 202;LUT 110 = 207;LUT 111 = 212;LUT 112 = 216;LUT 113 = 221;LUT 114 = 225;LUT 115 = 229;LUT 116 = 232;LUT 117 = 235;LUT 118 = 239;LUT 119 = 241;LUT 120 = 244;LUT 121 = 246;解调模块module depsk( clk,reset_n,data,dataout,); input clk ;input reset_n ;input 7 : 0 data; output 7:0dataout; reg 6 : 0 counter_value;reg 7:0 middata;always ( posedge clk or negedge reset_n )begin if(!reset_n) begincounter_value6:0=7b000_0000;/赋初值middata7:0=8b00000000;/寄存器赋初值 end else begin counter_value=counter_value+7b000_0001;/时钟沿依次加一if(counter_value=7b010_0000)begin middata7:0=data7:0;/如果读到的值等于32，则取采样值endelse beginmiddata7:0=middata7:0;/如果没有读到32，则取0值end endendassign dataout0=mid