FPGA-ARM通信代码.doc

libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; -FPGA内部寄存器地址定义： packageinterfaceis constantaddr_reg1:std_logic_vector(9downto0):=0000000000; constantaddr_reg2:std_logic_vector(9downto0):=0000000001; constantaddr_reg3:std_logic_vector(9downto0):=0000000010; constantaddr_reg4:std_logic_vector(9downto0):=0000000011; end; libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; erface.all; entityarm_fpgais port( mcudata:inoutstd_logic_vector(7downto0);-8位数据 mcuaddress:instd_logic_vector(9downto0);-10位地址 wr:instd_logic;-写信号 rd:instd_logic; cs:instd_logic; led:outstd_logic_vector(7downto0); end; architecturearmfpgaofarm_fpgais signaladdresstemp:std_logic_vector(9downto0);-内部寄存器 signaldatatemp1,datatemp2,datatemp3,datatemp4:std_logic_vector(7downto0); signalwr_en,rd_en:std_logic;-读写使能 begin addresstemp=mcuaddress; wr_en=(wrandrd)orwr; rd_en datatemp1 datatemp2 datatemp3 datatemp4null; endcase; endif; endif; endprocess; -ARM从FPGA读取数据： process(rd,rd_en) begin ifrdeventandrd=0then ifcs=0andrd_en=0then caseaddresstempis whenaddr_reg1= mcudata mcudata mcudata mcudatanull; endcase; endif; endif; endprocess; led=mcudata;-验证传输数据，LED显示 end;-mcufpga.vhd libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; -FPGA内部寄存器地址定义： packageinterfaceis constantaddr_reg1:std_logic_vector(9downto0):=0000000000; constantaddr_reg2:std_logic_vector(9downto0):=0000000001; constantaddr_reg3:std_logic_vector(9downto0):=0000000010; constantaddr_reg4:std_logic_vector(9downto0):=0000000011; end; libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; erface.all; entityarm_fpgais port( mcudata:inoutstd_logic_vector(7downto0);-8位数据 mcuaddress:instd_logic_vector(9downto0);-10位地址 wr:instd_logic;-写信号 rd:instd_logic; cs:instd_logic; led:outstd_logic_vector(7downto0); end; architecturearmfpgaofarm_fpgais signaladdresstemp:std_logic_vector(9downto0);-内部寄存器 signaldatatemp:std_logic_vector(31downto0); -signalwr_en,rd_en:std_logic;-读写使能 begin addresstemp=mcuaddress; -ARM写数据到FPGA： process(wr,cs) begin -datatemp1datatemp(7downto0)datatemp(15downto8)datatemp(23downto16)datatemp(31downto24)null; endcase; endif; endprocess; -ARM从FPGA读取数据： process(rd,cs) begin ifrdeventandrd=0andcs=0then -caseaddresstempis -whenaddr_reg1=mcudatamcudatamcudatamcudatamcudata=ZZZZZZZZ; mcudata= datatemp(7downto0)when(addresstemp=addr_reg1)else datatemp(15downto8)when(addresstemp=addr_reg2)else datatemp(23downto16)when(addresstemp=addr_reg3)else datatemp(31downto24)when(addresstemp=addr_reg4)else ZZZZZZZZ; endcase; endif; endprocess; led=mcudata; end;-mcufpga.vhd libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; entityarm_fpgais port( mcudata:inoutstd_logic_vector(7downto0);-8位数据 mcuaddress:instd_logic_vector(9downto0);-10位地址 wr:instd_logic;-写信号 rd:instd_logic; cs:instd_logic; led:outstd_logic_vector(7downto0); end; architecturearmfpgaofarm_fpgais signaladdresstemp:std_logic_vector(1downto0);-内部寄存器 signaldatatemp:std_logic_vector(31downto0); begin addresstemp=mcuaddress(1downto0); -ARM写数据到FPGA： datatemp(7downto0)=mcudatawhen(cs=0andwr=0andaddresstemp=00); datatemp(15downto8)=mcudatawhen(cs=0andwr=0andaddresstemp=01); datatemp(23downto16)=mcudatawhen(cs=0andwr=0andaddresstemp=10); datatemp(31downto24)=mcudatawhen(cs=0andwr=0andaddresstemp=11); -ARM从FPGA读取数据： mcudata=datatemp(7downto0)when(cs=0andrd=0andaddresstemp=00)else datatemp(15downto8)when(cs=0andrd=0andaddresstemp=01)else datatemp(23downto16)when(cs=0andrd=0andaddresstemp=10)else datatemp(31downto24)when(cs=0andrd=0andaddresstemp=11)else ZZZZZZZZ;-ZZ不可少,否则总线被FPGA锁死. led=mcudata; endarmfpga;libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; entityarm_fpgais port( mcudata:inoutstd_logic_vector(7downto0);-8位数据 mcuaddress:instd_logic_vector(9downto0);-10位地址 wr:instd_logic;-写信号 rd:instd_logic; cs:instd_logic; led:outstd_logic_vector(7downto0); end; architecturearmfpgaofarm_fpgais constantaddr_reg1:std_logic_vector(9downto0):=0000000000; constantaddr_reg2:std_logic_vector(9downto0):=0000000001; constantaddr_reg3:std_logic_vector(9downto0):=0000000010; constantaddr_reg4:std_logic_vector(9downto0):=0000000011; signaladdresstemp:std_logic_vector(9downto0);-内部寄存器 signaldatatemp:std_logic_vector(31downto0); -signalwr_en,rd_en:std_logic;-读写使能 begin addresstempdatatemp(7downto0)datatemp(15downto8)datatemp(23downto16)datatemp(31downto24) datatemp0); endcase; else datatemp0); endif;