网络变压器设计及工艺.doc

LAN Magnetics DesignIntroduction:The following presentation is a tutorial in the field of ferrite toroid designfocusing on the area of Local Area Networks (LAN). The formulas in thechapters are either standard magnetic pulse transformer design derivations,or personally derived estimating formulas for calculating the parasitic parameter values.There has been a attempt to create these formulas fromthe placement of wire on the toroidal core. This is not perceived as a perfectdepiction of the parameters, but as an estimate based upon the wire beingplaced upon the core evenly without the presence of winding errors such asgaps or wire crossovers. The results of these human winding variations would increase the calculated values. However, this paper presents a fairlyaccurate picture of the functional performance based upon the data inputs.These created formulas should be considered as a first cut at the design totry to save time. The final outcome is achieved when the finished coil designsare functionally tested and the design is fine tuned to meet the IEEE specific-ations. Copyright 2006 - Dallas DeanBiography:Dallas Dean has over forty years of experience working in the field of magnetic pulse transformer design. Designs include shift registers, counters,pulse transformers,filters, Token Ring and LAN magnetics to suppress EMI noise. As the electrical member of one design team, he holds two patents in shielded connector design. Dean holds a B.S. degree in electro- mechanical engineering from Lowell Technological Institute (Lowell University). He can be contacted via email at .Book Outline Chapter 1 - Design FlowchartChapter 2 - Specifications & RequirementsChapter 3 - Core selectionChapter 4 - Transformer DesignChapter 5 - Leakage InductanceChapter 6 - Coupling CapacitanceChapter 7 - Distributed CapacitanceChapter 8 - Winding DC ResistanceChapter 9 - Waveform AnalysisChapter 10 - Parasitic parameter optimizationChapter 11 - Common mode choke design CMIChapter 12 - Waveform calculationsChapter 1 LAN magnetics design procedureThe design procedure starts with the determination of what is needed for the electrical and mechanical requirements from the customer and the IEEE specifications.The mechanical requirements are dictated by the customers motherboard real estate area and board separations. This determines the physical size of the connector that the magnetic components occupy. The pin positions also control the useable area for the magnetics within the package. All this has to be addressed to best meet the electrical and EMI specifications of IEEE and the customer, especially near end crosstalk (NEXT) and common mode rejection. It is desirable to have a margin of about 0.050 inch distance from the buffered coil surface to the inside walls of the connector package. These constraints limit the size of the magnetics to be used.All printed circuit boards used in the connector should have short run traces of low resistivity for the best EMI performance. The input to output trace placement should be carefully observed to avoid cross talk and common mode signal problems.It is extremely important that the placement of the isolation capacitor and its traces be positioned such that the isolation voltage from the input to output of the transformer is maintained per the IEEE standards. Position of the wires to the magnetic coils in relation to the capacitor is important to both voltage isolation and EMI performance. The transformer electrical design should have a “worst-case analysis” performed, including low temperature requirements to achieve the minimum inductance at the lowest temperature and DC bias conditions of the ferrite material being used.After choosing a core size that will fit in the package, the number of turns is calculated to achieve the correct amount of minimum inductance on the core.The optimum wire size that will allow both windings on the core to fit the ID in one layer is then calculated. The nearness of the wire to the core limits the loss of flux lines due to winding coupling. This will achieve the best leakage inductance other than twisting the wire for better coupling between the windings. With these wires on the core, the maximum coil outside diameter and height with any buffer applied to the coil is then calculated. The coil parasitic parameters that this winding produces are also calculated. These would be: leakage inductance, coupling capacitance, distributed capacitance and DC winding resistance. These can be calculated using the formulas listed in the following chapters, the formula glossary or the use of the spreadsheet on the CD.The pulse waveform template is now addressed. Calculate the rise time, the low frequency pulse top droop, the fall time, the backswing and the recovery time. The fall time can be estimated to be the same as the rise time in most cases. These can be calculated using the formulas listed in the following chapters, the formula glossary or the use of the spreadsheet on the CD.Now these answers are checked against the requirements of IEEE and the customer. If they do not conform to them, then there have to be adjustments made. These can be as simple as changing the percentage cover on the core, twisting the wire, changing the wire gauge or perhaps the wire insulation thickness.The common mode choke is then designed to provide the maximum of attenuation for CMR in the frequency bandwidth of 30 to 1000 Mhz. Most of the noise problems will be observed at the harmonics of the clock frequency.It would be very helpful and time saving if data for both impedance and CMR attenuation were available for various turns and wire gauges for several Nickel-Zinc ferrite materials. This data could be integrated into a spreadsheet so that quick calculations could be run arriving at a coil solution that could be wound and tested for optimum performance. If a certain frequency is known to be a problem for EMI, then the impedance of the core should be at a peak at or above this frequency. The reason that a point above this frequency is chosen is due to the dielectric effect of the buffering material. The impedance peak will shift downward in frequency after the coating. Once a CM choke is chosen, then it is combined with the transformer and the pair is then tested for final CMR attenuation. When it is close to what is needed, the coils are coated with the buffer material and retested to see if the compensated dielectric change varied the frequency of peak attenuation to the problem frequency. When the final design is achieved, then the coated coil sets are wound and assembled into the connector and tested for Insertion Loss, Return Loss, Common Mode Rejection and Near End Crosstalk (NEXT). The results are then checked against the IEEE requirements. Limiting the wire lengths between the transformer and the CMI choke and adjusting the coil orientation may vary the crosstalk and the common mode rejection. When these specifications are achieved, then EMI is tested over the bandwidth both in an anechoic chamber and in an outside range using both 3 and 10-meter antennas. All these steps are shown on the following flow charts with the referenced chapters of formulas and examples.Chapter 2Specifications and RequirementsElectrical specifications are outlined in the IEEE 802.3 document. These values listed below are based upon the Draft supplement to IEEE Std. 802.3 Type 10BaseT issued on June 28,1990. A more current revision should be researched to get the most current specification data. Electrical:The Transmit transformer secondary winding minimum inductance is 350uh with 8ma. DC bias applied over 0o to +70oC.This inductance is needed to meet the waveform templates specified in 802.3.There shall be 1500 VRMS isolation between the input and output of the transformer.The rise time and fall time shall be between 3 and 5ns.There shall be no more than 5% overshootThe insertion loss shall be less than 1.0db between 1 to 100MhzThe return loss shall be greater than 15db over the frequency range of 5MHz to 10MHz with a resistive source of between 85 ohms to 111 ohms.The typical crosstalk between 1Mhz to 10Mhz should be better than 40db.The typical Common Mode Rejection between 1Mhz to 50Mhz should be better than 30db.Chapter 3 Core Size SelectionAfter the proper ferrite material is chosen to meet the extended temperature and DC bias conditions needed for this application, choose several size profiles from the vendors catalogs so that there will be a variety of choices to achieve all parameters and fit solutions.Choosing the correct size core to fit into the inner volume of a package or connector case depends upon the wire and buffer material build on the core sets as well as the number of core sets in the package.It is a good idea to allow a minimum margin of approximately 0.025 inch between the inside wall of the case cavity and the final buffered coil. Assuming that the buffering is about 0.020 inch, we can allow approximately 0.050 inch of margin from the cavity wall to the wire around the core. This can provide a close estimate to choose the closest outside diameter and height of a standard core from a vendors catalog. Once this core has been chosen, the turns and wire size can then be calculated from chapter 4. When these have been established, then the wire build on the core is calculated.The formulas for these calculations are as follows:The following formula is used to approximate the wire diameter needed to accommodate a bifilar winding on the core.The nearest HPN AWG size that will fit into the core ID is:(Round off this to lowest value)Chapter 6 references formulas used to determine HPN, TPN and QPN wire diameters.To estimate the coil outside diameter (OD) for HPN wire use the following relationship:Where: Now estimate the coil height (H) for HPN wire with:Choosing either TPN or QPN wire to improve the hipot withstanding voltage, will probably produce a coil of larger dimensions. The additional polyurethane coating on the wire will force this issue. If this is the case, perhaps it is best to use the next smaller diameter wire, if that is within the winding reliability guidelines. Smaller wire can become brittle and break with soldering heat and assembly movements.Coil orientation in packageAfter the coils are wound, it is very important to keep the wire lengths between the transformer and the common mode choke as short as possible to minimize EMI radiation and keep the leakage inductance as low as possible for rise time and return loss considerations. At times, it is difficult to achieve the proper orientation because of the cavity constraints. This may have to be negotiated with the mechanical engineering group designing the package early in the design stage. A compromise may have to be met. Crosstalk considerationsTo provide the best crosstalk in the connectors, it is best to separate the coil sets as far away from each other as possible. This can be a problem most of the time because of the inside cavity constraints and the number of coils needed for the ports.The winding start and finish window of the common mode choke coil should face away from the common mode choke of the next channel so that there is no linkage of the leakage flux between the channels.Dress the leads of one channel as far away from the adjacent channel leads as possible to avoid coupling. Any added capacitance from close leads will only add to crosstalk problems.Using the crosstalk estimating spreadsheet on the CD will provide a guide as to the effect of varying distances between coils or wires.Common Mode Rejection considerationsTo achieve the best common mode rejection, it is best to focus on the wire dress. Keep the wire lengths short but still allow proper stress relief in the leads to prevent wire breakage due to movement. Fine wire can be very brittle, especially after undergoing a soldering operation. The heat tends to destroy the ductility of the wire by changing the copper hardness. Maintain the common mode choke winding start and finish as far away from each other as possible. A coil cover of 300 degrees or less is an acceptable maximumThe transformer coil should be perpendicular to the common mode choke for the best common mode rejection ratio. Again, keep the wire length between the transformer and the common mode choke as short as possible.Buffering MaterialsIt is very important that the transformer coils be coated with a buffering material to prevent any chance of magnetostriction caused by epoxy or the package. It is important, however, to prevent too much buildup of the material. It may be better to thin the buffering material with a proper solvent and use multiple coats on the cores. The addition of buffering material increases the distributed and the interwinding capacitance on the transformer proportional to the dielectric constant of the buffer.When the common mode choke is coated with buffering material, then the distributed capacitance of the coil is increased by the materials dielectric constant. Thus, the resonant frequency decreases. This in turn lowers the peak frequency of the impedance curve and may definitely change the EMI attenuation response of the circuit. This is one reason why the choke peak should be adjusted by an appropriate amount above the desired frequency of attenuation.There are many buffering materials to be found in the marketplace, but the most useful are the silicones. Their expansion rates can be less and the dielectric constants are acceptable. Isolation Voltage considerationsThe main concern with the coil set hipot is found between the primary and secondary windings of the transformer. There is no hipot problem with the transformer secondary and the common mode choke. They are at the same potential. This can be controlled by the choice of the wire insulation thickness. Usually the QPN or TPN wire is thick enough to provide a good margin for the 1500 VRMS required by IEEE. There should be care given with the wire termination so that the transformer primary wires should not be near the output from the common mode choke. This includes any component or termination that may be close to either one. Care should be exercised to keep the high potential wires away from any ground connections or capacitors that may be near ground potential. The layout of the PC board traces should also consider this danger.Chapter 4Transformer DesignAs mentioned in chapter 3, the coil size is determined by the size constraints of the module package inside dimensions.A worst case analysis is best performed on the design to arrive at the desired inductance to design to so that the minimum inductance of 350uh is met after the core tolerance, DC bias effects and temperature variation are considered. After reviewing all core vendors manganese zinc materials and choosing the ones that had the best characteristics for temperature and coercive force, then the design inductance can be established. To estimate the number of turns that will be used on the core, start with calculating the core constant needed to fit in the package.K= AC / lm N = Lmin /uK0.5Example:Assume K=0.10725 N= 350 * 10-6 / 4500 * .10725 0.5N = 26 turnsWith an initial estimate of the number of turns, it is now time to calculate the coercive force that 8 ma of DC bias will produce with these turns on that size core.H= 0.4 * 3.14159 * 26 * 0.008 / 0.894 = 0.2924 oerstedsFrom the chosen vendors catalog, find the flux density that is available with the DC bias applied and the new permeability that the temperature variation causes.Worst Case Analysis:Minimum OCL = 350uh.Allowing for 15% DC bias drop over 0C to +70C, 350/0.85 = 411.7uh. Allowing for 20% core tolerance, 411.7/0.8 = 514.7uh nominalExample:N = 350 * 10-9 / (4500*.80*.85) * .10725 = 34 turnsThese turns are a bit high to meet all the parasitics so we will have to adjust the size of the core. Possibly by raising the core height.N = 350 * 10-9 / (4500*.80*.85) * .17 = 26 turnsIf this is not acceptable, then the OD or ID of the toroid as well as the height will have to be adjusted to the next available size, or request the core vendor make a special tooling. Chapter 5 Leakage InductanceThe leading parameter controlling the slope of the pulse rise time passing through a transformer is leakage inductance. The rise time is directly proportional to the leakage inductance magnitude by inspection of the rise time estimator equation:The leakage inductance factor in the numerator is a magnitude greater than the distributed capacitance factor. The leakage inductance is typically in nanohenries (10-9) and distributed capacitance is in picofarads (10-12). Leakage inductance is a larger magnitude value. Leakage inductance is the remaining inductance of the coil after the open circuit inductance OCL is removed by shorting out the secondary winding and measuring the primary winding. This leaves the wire inductance and remaining lines of flux lost to the air by the poor coupling of the windings to each other. Model:CalculationsLeakage inductance, Ll, as it appears in relation to other transformer parameters is shown in the previous model. All secondary parameters are reflected back to the primary side by the turns ratio squared. Calculations are performed on the parameters as they ap