用VHDL语言实现拔河电路功能

.实验四 基于Quartus 的硬件描述语言的拔河电路设计1、 实验内容基于前期原理图电子拔河电路，甲、乙双方分别按动己方按键，按键的次数分别在双方的两个数码管上显示，当喊停止的时候，数码管数字较大的一方获胜，连续比赛多局以定胜负。二、实验工具1、DE0开发板一个2、Quartus 2 16软件3、VHDL语言三、实验准备1、学习VHDL语言，了解基本语法规则和基本语句。2、明确所实现的电路所需要的器件，并且明确用VHDL实现该器件的基本逻辑关系和基本语句。实验所需要的器件为百进制计数器、比较器和译码器。3、明确VHDL实体的定义，明确实体的输入输出，并且明确实现该实体的基本语法和基本步骤。4、必须明确实体层次的概念，在低层次实体中，必须明确各个输入输出之间的联系，以结构的方式构建高层次实体。四、实验程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY test4 ISPORT(KEY1,KEY2,KEY3,CLOCK_IN: IN STD_LOGIC; HEX0,HEX1,HEX2,HEX3,HEX4,HEX5: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); com:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END test4;-以下为百进制计数器设计实体-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT_100 ISPORT(clk,clr: IN STD_LOGIC; -date_in: IN STD_LOGIC_VECTOR(3 DOWNTO 0); lo_out,hi_out:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNT_100;ARCHITECTURE fwm OF COUNT_100 ISSIGNAL hi_tmp,lo_tmp: STD_LOGIC_VECTOR(3 DOWNTO 0);-SIGNAL load_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN-load_cnt=load&hi_lo; -数据写入与置数位控制的并置PROCESS(clk,clr) -hi_lo=1时为高位置数，hi_lo=0时为低位置数-VARIABLE q_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF clr=0THEN hi_tmp=0000;lo_tmp=1010 THEN lo_tmp=1001;-ELSE lo_tmp=1010 THEN hi_tmp=1001;-ELSE hi_tmp=date_in;-END IF;-ELSIF load_cnt=01 OR load_cnt=00 THENIF lo_tmp=1001 THEN -低位等于9IF hi_tmp/=1001 THEN -如果高位不等于9lo_tmp=0000; hi_tmp=hi_tmp+1; -那么高位加1ELSE hi_tmp=0000;lo_tmp=0000; -ELSE lo_tmp=1001; -除此之外，低位9保持不变END IF;ELSE lo_tmp=lo_tmp+1; -如果低位不是9，那么低位加1END IF;-END IF;END IF;END PROCESS;lo_out=lo_tmp; -低位信号赋值给低位输出端hi_out=hi_tmp; -高位信号赋值给高位输出端END fwm;-以下为计算胜的局数的10进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT_10 ISPORT(clk,clr: IN STD_LOGIC; COUNT_10_OUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNT_10;ARCHITECTURE fwm OF COUNT_10 ISSIGNAL COUNT_10_TMP: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk,clr)BEGIN IF clr=0THEN COUNT_10_TMP= 0000; -异步清零ELSIF clkEVENT AND clk=1THENCOUNT_10_TMP=COUNT_10_TMP+1;IF COUNT_10_TMP=1001 THEN -如果加到十，归零COUNT_10_TMP=0000;END IF;END IF;END PROCESS;COUNT_10_OUT=COUNT_10_TMP;END fwm; -以下为分频器实体电路LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FP ISPORT(clk_in:IN STD_LOGIC;clk_out:OUT STD_LOGIC);END FP;ARCHITECTURE fwm OF FP ISCONSTANT M:INTEGER:=25000000; -50M分频到1HZSIGNAL FP_TMP:STD_LOGIC;BEGIN PROCESS(clk_in)VARIABLE COUNT :INTEGER:=0;BEGIN IF clk_inEVENT AND clk_in=1 THENCOUNT:=COUNT+1; -计数器+1IF COUNT=M THEN FP_TMP=0;ELSIF COUNTM*5 THEN FP_TMP=1;ELSE COUNT :=0;END IF;END IF;END PROCESS;clk_out dis_out dis_out dis_out dis_out dis_out dis_out dis_out dis_out dis_out dis_outdis_out=1111111; -不显示；END CASE;END PROCESS;END fwm; -以下为8位无符号整数比较器设计实体LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COMPARE ISPORT(a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);eq,lt,gt: OUT STD_LOGIC);END COMPARE;ARCHITECTURE fwm OF COMPARE ISBEGINPROCESS(a,b)BEGINeq=0;lt=0;gt=0;IF a=b THEN eq=1;END IF;IF ab THEN ltb THEN gtCLOCK_IN,clk_out=CLK_OUT);U1: COUNT_100 PORT MAP(clk=KEY1,CLR=CLK_OUT, lo_out=tem_lo_1, hi_out=tem_hi_1);U2: COUNT_100 PORT MAP(clk=KEY2,CLR=CLK_OUT, lo_out=tem_lo_2, hi_out=tem_hi_2); U3: DIS PORT MAP(date_in=tem_lo_1, dis_out=HEX0);U4: DIS PORT MAP(date_in=tem_hi_1, dis_out=HEX1);U5: DIS PORT MAP(date_in=tem_lo_2, dis_out=HEX2);U6: DIS PORT MAP(date_in=tem_hi_2, dis_out=HEX3); U7: COMPARE PORT MAP(a(0)=tem_lo_1(0),a(1)=tem_lo_1(1),a(2)=tem_lo_1(2),a(3)=tem_lo_1(3), a(4)=tem_hi_1(0), a(5)=tem_hi_1(1), a(6)=tem_hi_1(2), a(7)=tem_hi_1(3),b(0)=tem_lo_2(0),b(1)=tem_lo_2(1),b(2)=tem_lo_2(2),b(3)=tem_lo_2(3), b(4)=tem_hi_2(0), b(5)=tem_hi_2(1), b(6)=tem_hi_2(2), b(7)=tem_hi_2(3),lt=lt_mid,eq=eq_mid,gt=gt_mid); U8: COMPARE PORT MAP(a(0)=tem_lo_1(0),a(1)=tem_lo_1(1),a(2)=tem_lo_1(2),a(3)=tem_lo_1(3), a(4)=tem_hi_1(0), a(5)=tem_hi_1(1), a(6)=tem_hi_1(2), a(7)=tem_hi_1(3),b(0)=tem_lo_2(0),b(1)=tem_lo_2(1),b(2)=tem_lo_2(2),b(3)=tem_lo_2(3), b(4)=tem_hi_2(0), b(5)=tem_hi_2(1), b(6)=tem_hi_2(2), b(7)=tem_hi_2(3),lt=COM(0),eq=COM(1),gt=COM(2);U9: COUNT_10 PORT MAP(clk=lt_mid,clr=KEY3,COUNT_10_OUT=COUNT_10_DATE_OUT1);U10: COUNT_10 PORT MAP(