通用寄存器组.doc

library ieee;use ieee.std_logic_1164.all;entity decoder_3_8 is port(I_L:in std_logic_vector(2 downto 0);S1,S2_L,S3_L:in std_logic;F_L:out std_logic_vector(7 downto 0);end decoder_3_8;architecture decoder_3_8p of decoder_3_8 is signal F_s :std_logic_vector(7 downto 0);begin process(I_L,S1,S2_L,S3_L)begin case I_L iswhen 000 = F_s F_s F_s F_s F_s F_s F_s F_s F_s =11111111;end case;if (S1 and not S2_L and not S3_L)=1 then F_L = F_s;else F_L = 11111111;end if;end process;end decoder_3_8p;-底层16位寄存器library ieee;use ieee.std_logic_1164.all;entity register16 isport(clk,clear,cs,wr:in std_logic;d: in std_logic_vector(15 downto 0);q: out std_logic_vector(15 downto 0); end entity register16;architecture registerp of register16 issignal qin : std_logic_vector(15 downto 0);begin process(clk,clear,cs,wr,qin)beginif clear = 0 thenqin = 0000000000000000;elsif rising_edge(clk) thenif wr = 0 and cs = 0 thenqin = d;end if;end if;if cs = 0 and wr = 1 then q = qin;elseqsta,S2_L=stb,S3_L=stc,I_L(0)=C(0),I_L(1)=C(1),I_L(2)=C(2),F_L(0) = t(0),F_L(1) = t(1),F_L(2) = t(2),F_L(3) = t(3),F_L(4) = t(4),F_L(5) = t(5),F_L(6) = t(6),F_L(7) = t(7);g2:register16 port map(clk = clk2,clear = clear2,cs = t(0),wr = wr2,d=A,q=B);g3: register16 port map(clk = clk2,clear = clear2,cs = t(1),wr = wr2,d = A,q = B);g4: register16 port map(clk = clk2,clear = clear2,cs = t(2),wr = wr2,d = A,q = B);g5: register16 port map(clk = clk2,clear = clear2,cs = t(3),wr = wr2,d = A,q = B);g6: register16 port map(clk = clk2,clear = clear2,cs = t(4),wr = wr2,d = A,q = B);g7: register16 port map(clk = clk2,clear = clear2,cs = t(5),wr = wr2,d = A,q = B);g8: register16 port map(clk = clk2,clear = clear2,cs = t(6),wr = wr2,d = A,q = B);g9: r