基于VHDL的IIC时序电路设计.doc

基于VHDL的IIC时序电路设计iic 总线在设计时要看你所使用的器件的传输或接收时序只要会一个，其他的都一样以下是我在一本书上看到的，你看看就会用了library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity reciver isport(reset,clk:in std_logic;sda,scl:inout std_logic;rd:out std_logic;tdata:in std_logic_vector(7 downto 0);rdata:out std_logic_vector(7 downto 0);end reciver;architecture one of reciver issignal rdatai:std_logic_vector(7 downto 0);type state is (start,transmit,ack,sub,ack1,start1,slave,ack2,reading,ack3);signal current:state;beginprocess(clk,reset)variable count:integer range 0 to 40;variable cnt:integer range 0 to 8;beginif reset=1thensda=1;scl=1;rdata=00000000;currentcount:=count+1;case count iswhen 1=sdasclsdasclcount:=0;currentnull;end case;when transmit=count:=count+1;case count iswhen 1=sdasclsclcnt:=cnt-1;count:=0;if cnt=0 then cnt:=8;current=ack;rd=1;else current=transmit;rdnull;end case;when ack=count:=count+1;case count iswhen 1=sdasclsclcurrentnull;end case;when sub=count:=count+1;case count iswhen 1=sdasclsclcnt:=cnt-1;count:=0;if cnt=0 then cnt:=8;current=ack1;rd=1;else current=sub;rdnull;end case;when ack1=count:=count+1;case count iswhen 1=sdasclsclcurrentnull;end case;when start1=count:=count+1;case count iswhen 1=sdasclsdasclcurrentnull;end case;when slave=count:=count+1;case count iswhen 1=sdasclsclcnt:=cnt-1;count:=0;if cnt=0 then cnt:=8;current=ack2;rd=1;else current=sub;rdnull;end case;when ack2=count:=count+1;case count iswhen 1=sdasclsclcurrentnull;end case;when reading=count:=count+1;case count iswhen 1=sdasclrdatai(cnt)sclcnt:=cnt-1;count:=0;if cnt=0 then cnt:=8;current=ack3;rd=1;else current=reading;rdnull;end case;when ack3=count:=count+1;case count iswhen 1=sdasclsclrdata=rdatai;currentnull;end case;end case;end if;end process;end arc