数字钟vhdl代码.doc

libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityshuzizhongis port(clk:instd_logic;时钟信号 choose,set,s1,s2:instd_logic;12/24 时制选择，设置，时设置，分设置 am,pm,spk:outstd_logic;上午，下午，报时信号 b:outstd_logic_vector(6downto0);七段数码管 cat:outstd_logic_vector(5downto0)数码管选通控制信号 ); endshuzizhong;architectureaofshuzizhongis signalhou1:integerrange0to23;24 时制小时信号 signalhou2:integerrange0to11;12 时制小时信号 signalmin:integerrange0to59;分信号 signalsec:integerrange0to59;秒信号 signaltemp:integerrange0to19; signalclk0:std_logic;计时时钟信号 signaltmp:integerrange0to999999; signala:std_logic_vector(1downto0); typestrisarray(0to5)ofintegerrange0to9;定义整型数组 signaltimeout:str; signalcount:integerrange0to5; begin p1:process(clk)分频模块 begin ifclkeventandclk=1then iftmp=999999then1M 分频； tmp=0; else tmp=tmp+1; endif; iftmp500000thenclk0=0; else clk0=1; endif; endif; endprocessp1; p2:process(clk0,choose,set,s1,s2) begin ifclk0eventandclk0=1then ifset=0then计时模块 sec=sec+1;秒计时ifsec=59then sec=0;秒进位 min=min+1;分计时 ifmin=59then min=0; hou1=hou1+1;24 小时进制小时位计时 ifhou1=23then hou1=0; endif; hou2=hou2+1;12 小时进制小时位计时 ifhou2=11then hou2=12then a=01; elsifhou112then a=10; endif; elsea=00; endif; elsifset=1then设置时间模式 ifs2=1then设置分 ifmin=59then min=0; else min=min+1; endif; endif; ifs1=1then设置时 hou1=hou1+1;24 时制 ifhou1=23then hou1=0;endif; hou2=hou2+1;12 时制 ifhou2=11then hou2=12then a=01; elsifhou112then a=10; endif; elsea=00; endif; endif; endif; ifmin=0then整点报时 iftimeout(0)=5andtimeout(1)=0then蜂鸣器响5 秒 spk=1; else spk=0; endif; else spk=0; endif; endif; endprocessp2; p3:process(clk,choose)译码显示模块 begin timeout(0)=secrem10;秒后一位 timeout(1)=sec/10;秒前一位 timeout(2)=minrem10;分后一位 timeout(3)=min/10;分前一位 ifchoose=0then根据choose 信号选择输出时制 timeout(4)=hou2rem10;timeout(5)=hou2/10; elsifchoose=1then timeout(4)=hou1rem10; timeout(5)=hou1/10; endif; ifclkeventandclk=1then ifcount=5then count=0; else countcat=011111;tempcat=101111;tempcat=110111;tempcat=111011;tempcat=111101;tempcat=111110;tempcat=111111;tempbbbbbbbbbbb=0000000;错误，输出0 endcase; endprocessp3; am=a(1); pm=a(0); enda; library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shuzizhong is port( clk:in std_logic; clear:in std_logic; choose:in std_logic; c:out std_logic_vector(6 downto 0); cat:out std_logic_vector(5 downto 0) ); end shuzizhong; architecture b of shuzizhong is signal tmp1:integer range 0 to 49999; signal tmp2:integer range 0 to 99999; signal m_flag,s_flag:integer range 0 to 59; signal h_flag1:integer range 0 to 23; signal h_flag2:integer range 0 to 11; signal clk1:std_logic; signal temp: integer range 0 to 19; type str is array(0 to 5)of integer range 0 to 9; signal timeout:str; signal count:integer range 0 to 5;begin p1:process(clear,clk) begin if clear=0 then tmp1=0; elsif clkevent and clk=1 then if tmp1=49999 then tmp1=0; else tmp1=tmp1+1; end if; if tmp1=49999 then tmp2=tmp2+1; if tmp2=9999 then tmp2=0; end if; end if; end if; end process p1; p2:process(tmp2) begin if tmp2=99999 then clk1=1; else clk1=0; end if; end process p2; p3:process(all) begin if clk1event and clk1=0then s_flag=s_flag+1; if s_flag=59 then s_flag=0; m_flag=m_flag+1; if m_flag=59 then m_flag=0; h_flag1=h_flag1+1; if h_flag1=23 then h_flag1=0; end if; h_flag2=h_flag2+1; if h_flag2=11 then h_flag2=0; end if; end if; end if; end if; end process p3; p4:process(clk,choose) begin timeout(0)=s_flag rem 10; timeout(1)=s_flag/10; timeout(2)=m_flag rem 10; timeout(3)=m_flag/10; if choose=0 then timeout(4)=h_flag2 rem 10; timeout(5)=h_flag2/10; elsif choose=1 then timeout(4)=h_flag1 rem 10; timeout(5)=h_flag1/10; end if; if clkevent and clk=1 then if count=5