模60的加法器四位计数器 异步复位JK触发器同步D触发器.doc

module MUX_4(out,in0,in1,in2,in3,sel); output out; input in0,in1,in2,in3; input1:0 sel; /定义sel输入/ reg out; always(in0 or in1 or in2 or in3 or sel) begin if(sel=2b01) out=in0; else if (sel=2b01) out=in1; else if (sel=2b10)/判断sel的值/ out=in2; else out=in3;endendmodule模60的加法器module JSQ60(qout,cout,data,load,cin,reset,clk); output7:0 qout; output cout; input7:0 data; input load,cin,clk,reset; reg7:0 qout; / 定义qout为寄存器/ always (posedge clk) begin if (reset) qout=0; else if(load) qout=data;else if(cin)begin if(qout3:0=9)/个位已经到9了/begin qout3:0=0; if (qout7:4=5) qout7:4=0;/十位过5，清零/ elseqout7:4=qout7:4+1; end else qout3:0=qout3:0+1;end end assign cout=(qout=8h59)&cin)?1:0;/当计数器满59且使能端为1，进位端输出1；/Endmodule看图描述module MUX4(Z,D0,D1,D2,D3,S0,S1); output Z; input D0,D1,D2,D3,S0,S1; wire T0,T1,T2,T3,S0f,S1f; and u0(T0,D0,S0f,S1f); and u1(T1,D1,S0f,S1f); and u2(T2,D3,S0,S1f); and u3(T3,D3,S0,S1); not u4 (S0f,S0); not u5 (S1f,S1); or u6(Z,T0,T1,T2,T3);endmodule 四位计数器 异步复位module johnson(clk,clr,out); input clk,clr; output3:0out; reg3:0out; /将out设置为寄存器型/ always(posedge clk or posedge clr) begin if(clr)out=4h0;/即执行清零操作 即输出全0/ else begin out=out1; out0=out3; end end EndmoduleJK触发器module JKCFQ(Q,J,K,CLK,RD); input J,K,CLK,RD; output Q; /把Q设置为输出/ reg Q; always(posedge CLK or negedge RD) begin if(!RD)Q=1B0; else case(J,K) 2b00:Q=Q;2b01:Q=1b0;/Q置0/ 2b10:Q=1b1;/Q置1/ 2b11:Q=Q; default: Q=1bx; endcase endendmodule 同步D触发器module DFF2(q,qn,d,clk,set,reset); input d,clk,set,reset; output q,qn; reg q,qn; always(posedge clk) begin if(reset) begin q=0;qn=1;/当reset为1 q为0 qn为1/ end else if(set) begin q=1;qn=0;/当set为q置1 qn置1/ end else begin q=d;qn=d;/当有时钟 但是set reset都是0的情况下；q=d qn等于d非/ end end Endmodule74ls138(38译码器)；module ls138(Y,A,G1,G2); output 7:0 Y; output 2:0 A; input G1,G2; reg 7:0 Y; wire G; assign G=G1&G2; always (A or G1 or G2) begin if(G) case (A) 3d0:Y=8b11111110; 3d1:Y=8b11111101; 3d2:Y=8b11111011; 3d3:Y=8b11110111; 3d4:Y=8b11101111;