数字设计——原理与实践第四版习题答案第6章.doc

6.2 DeMorgan equivalent symbol for a 7430 8-input NAND gate 6.3 DeMorgan equivalent symbol for a 7427 3-input NOR gate6.9 156=90ns6.20(a) F=X,Y,Z(2,4,7) U174HC138Y015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U2A74HC10R1VCCGNDZYX(b) F=A,B,C(3,4,5,6,7)U174HC138Y015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U2A74HC10R1VCCGNDABC(c) F=A,B,C,D(0,2,10,12)U174HC138N_4VY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U2A74HC20N_4VR11kVCC5VGNDABCDF(d) F=W,X,Y,Z(2,3,4,5,8,10,12,14)(e) F=W,X,Y(0,2,4,5), G=W,X,Y(1,2,3,6)(f) F=A,B,C(2,6), G=C,D,E(0,2,3)6.21 When the EN_L signal is asserted, the two part of the 74xx139 will be chosen simultaneously and it will cause fighting in the party-line. we could add an inverter to either of the enable input 1G_L or 2G_L to solve this problem.6.22 74ls138: g1- out 38ns G2a_l,G2b_l - out 32ns Any select-out 41ns 74ls151: any selectY 32ns Any data Y 20ns Enable Y 30ns 74ls20: 15nsThe maximum propagation delay =41+32+15=88ns6.24 Even number of xnor gatesOne xnor gateIts an even-parity circuit. 6.38 Truth bableinputoutputABCDY9Y8Y7Y6Y5Y4Y3Y2Y1Y0000000000000010001000000001000100000000100001100000010000100000001000001010000100000011000010000000111001000000010000100000000100110000000001010dddddddddd1011dddddddddd1100dddddddddd1101dddddddddd1110dddddddddd1111dddddddddd11d111d111dd11ddYi(i=09)ABCDY9=ADY8=ADY7=BCDY6=BCDY5=BCDY4=BCDY3=BCDY2=BCDY1=ABCDY0=ABCD6.43 6.50I9I8I7I6I5I4I3I2I1I0Y3Y2Y1Y010000000001111010000000011100010000000011100010000000110000010000001010000010000010000000010000011000000010000100000000010000100000000010000Y3=I9+I8Y2=I9+I8+I7+I6+I5+I4Y1= I9+I8+I7+I6+I3+I2Y0= I9+I7+I5+ I3+I16.51 NAND=NOT-ORI15I14I13I12I11I10I9I8I7I6I5I4I3I2I1I0DCBA01111011100110101100010110101001001010000011100110001010010000011000100000100000D=I15+I14+I13+I12+I11+I10+19+18C= I15+I14+I13+I12+I7+I6+I5+I4B= I15+I14+ I11+I10+ I7+I6+I3+I2A= I15 +I13+I11 +19+ I7 +I5 +I3+I16.52 6.53 U174LS148NA09A17A26GS14D313D41D52D212D111D010D74D63EI5EO15EI_LI7_LI6_LI5_LI4_LI3_LI2_LI1_LI0_LA0A1A2AVALIDEOU2A74HC05N_4V6.63 truth table: let S1,S0 to be select signals, A0:4, B0:4, C0:4 are the 5-bit input data, Y0:4 is the output.INPUTOUTPUTS1S0Y0Y1Y2Y3Y400A0A1A2A3A401B0B1B2B3B410C0C1C2C3C41100000Y0=S1S0A0+S1S0B0+S1S0C0Y1=S1S0A1+S1S0B4+S1S0C1Y2=S1S0A2+S1S0B2+S1S0C2Y3=S1S0A3+S1S0B3+S1S0C3Y4=S1S0A4+S1S0B4+S1S0C4S1S1A0A1A2A3A4B0B1B2B3B4C0C1C2C3C4Y0Y1Y2Y3Y4VCCGND6.74 Selecting circuitPQRTS2S1S0SASBY33